05-22-2012 05:41 AM
We've ported uboot and linux on microblaze for a SPARTAN6 device.
we've a BRAM code @ reset vector (0x0) which copies the uboot code from SPI flash to RAM and executes the uboot. same way uboot copies Linux image from SPI Flash to RAM and bootsup.
The problem is when we press the hard reset button.
the hard reset of the FPGA resets the Microblaze ONLY when we boots up kernel. Can we suspect the exception handler code in MB bootloop of xilinx ? are we missing something in the setup ?
05-22-2012 07:54 AM
Are you using the Xilinx reference design (hardware) for that board or building your own?
I would think that the reset is hooked up to reset the whole system rather than just he MicroBlaze.
05-22-2012 09:08 PM
Its a custom board.
Reset is supposed to reset the FPGA (and microblaze) and the bitfile configuration has to happen again..rite ?
we've not modified the linker script generated by xilinx. As we see it is getting reseted after kernel boots up, is it because of some linker script issue of BRAM code ?