05-29-2012 05:29 AM
Hi everyone, I already contacted support about this but thought it could be interesting to see if the "Linux on Zynq" community has any input.
I'm trying to reload a FPGA bitfile using the Xilinx Linux xdevcfg driver, essentially by just cat:ing the ("bit reversed") bitfile into the /dev/xdevcfg device file. Commit messages for the xdevcfg driver in the Xilinx git repo seems to indicate that this should work. (link)
However, after doing this the prog_done signal is never asserted again, so it's not working for me. The same bitfile (without bit reversing) works fine if loaded by the first stage bootloader or via JTAG.
Has anyone got this working?
Solved! Go to Solution.
05-29-2012 06:02 AM
mknod /dev/xdevcfg c 259 0
cat top.bit.bin > /dev/xdevcfg
The reason the file is top.bit.bin is because I use bootgen with the -split option to do the bit reversing.
05-29-2012 06:08 AM
Thank you for you very speedy ansver :)
This is exactly how I did my attempt, except that I used another bit file. Hence, there must be something wrong with my bit file.
Do you have any pointers on on how to convert a "normal" bit file (that works with fsbl and JTAG loading) to the proper xdevcfg format, using the Xilinx Design Tools for Windows (or other tools?). I'm pretty sure I missed something here.
Thanks in advance,
05-29-2012 07:01 AM
As I previously mentioned, use -split option of bootgen. So something like the following:
bootgen –image bootimage.bif –split bin –o I boot.bin
This will create a top.bit.bin (or whatever the bitfile is). You mention FSBL so I presume you already have a .bif file and have created BOOT.BIN
05-30-2012 10:55 AM
Will this driver be submitted to the upstream kernel?
Also, could we extend it to bit bang load (or use a spi controller to move data) fpga's attached to external processors? I can point you at another driver that uses that to load external fpga's.
05-31-2012 08:33 AM
I'm a collegue of Johan and as he said we succeeded loading the FPGA using /dev/xdevcfg in linux on the evaluation board zc702 Rev C.
The problem is that we have not succeded on our custom boards yet. We have not been able to load the FPGA from neither the FSBL or /dev/xdevcfg. We have only succeded using iMPACT + JTAG. Since we can load the FPGA via JTAG the bit file must be ok.
The error message from FSBL indicates that there is an FPGA config time out.
Do you have any good ideas on what can cause these problems? Can it be a board design issue?
Please give us some advise on how to solve this issue.
05-31-2012 03:49 PM
Sounds like you should open a web case for this problem. I doubt it's a board issue but could be something is configured wrong due to different clock frequencies, etc...
05-31-2012 03:52 PM
At some point yes we hope to get to pushing upstream again. I think the driver would be completely different for an external FPGA as this uses a Zynq specific engine to load the data.
06-04-2012 03:45 AM
We might have found the root cause on our custom boards. When we designed our boards we used the february version of the UG865 document which says that pin R6 on our XC7Z020-1CLG-400CES is RSVDGND. In the new version of UG865 pin R6 is RSVDVCC.
We have connected R6 to ground.
Johnmcd and linnj: What do you think, is it likely that this is the root cause?
We will try to patch our custom boards, but since we have to lift the BGA it is a high risc operation and it might take some time.