I just wanted to test the AXI Uart Lite IP with a small system.
In EDK the system is fairly simple:
- Microblaze
- 3 gpio componentes (leds, switches, buttons)
- interrupt controller
- timer controller
- uart lite
I implemented the system.xmp in the ISE14.1 suite and created an top module to adapt it to the Digilent Atlys Board.
After starting SDK and using hello_world demo the output seems fine. I can poll the uart lite rx_buffer for new data and receive it just fine.
My problem is:
int main(void) {
int ii = 0;
int jj = 0;
int kk = 0;
int init;
xil_printf("\n\r *** Start Main ***\n\r");
ii = Xil_In32(XPAR_UARTLITE_1_BASEADDR + 0x8);
xil_printf("%x",ii);
ii = Xil_In32(XPAR_UARTLITE_1_BASEADDR + 0x0);
xil_printf("%x",ii);
return 0;
}
In debug Mode, step by step:
*** Start Main ***
40
(everthing seems fine)
In normal Mode (program with bootloop):
*** Start Main ***
80
(tx buffer full)
What is wrong? The program does not do anything except readout of the registers. So the buffer should not be full?
