Embedded Processors and Peripherals

[lobe]

Are there any good example designs showing how to add a PCIE core to an existing microblaze design on my SP605 board.

I have been struggling to make this work, most issues with setting the correct AXI bus connections.

I know about the PLB bus examples, but I am looking for help with AXI.

Thanks you

[nanz]

Hi,

Here is an example:

http://www.xilinx.com/support/answers/43677.htm

In 13.4 BSB, PCie should be there too.

Thanks,

Nan

[lobe]

Thank you very much, let me try it and then will accept as a solution.

Laurence

[lobe]

When attempting to get this working since upgrading to 13.4, the Microblaze always shows it is "under RESET". This was working in 12.x.

Any help is much appreciated

I checked the clock and reset pins and I believe they are correct for the SP605.

I used the BSB to create a new design and added the PCIE to the Microblaze.

Note! I cannot get any Microblaze BSB designs to work on 13.4

c:\development\Xilinx\generic-sp605\lobemb\mblaze_0\data>type mblaze_0.ucf
#
# pin constraints
#
NET CLK_N LOC = "K22"  |  DIFF_TERM = "TRUE"  |  IOSTANDARD = "LVDS_25";
NET CLK_P LOC = "K21"  |  DIFF_TERM = "TRUE"  |  IOSTANDARD = "LVDS_25";
NET DIP_Switches_4Bits_TRI_I[0] LOC = "C18"  |  IOSTANDARD = "LVCMOS25";
NET DIP_Switches_4Bits_TRI_I[1] LOC = "Y6"  |  IOSTANDARD = "LVCMOS25";
NET DIP_Switches_4Bits_TRI_I[2] LOC = "W6"  |  IOSTANDARD = "LVCMOS25";
NET DIP_Switches_4Bits_TRI_I[3] LOC = "E4"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_COL LOC = "M16"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_CRS LOC = "N15"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_MDC LOC = "R19"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_MDIO LOC = "V20"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_PHY_RST_N LOC = "J22"  |  IOSTANDARD = "LVCMOS25"  |  TIG;
NET Ethernet_Lite_RXD[0] LOC = "P19"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_RXD[1] LOC = "Y22"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_RXD[2] LOC = "Y21"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_RXD[3] LOC = "W22"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_RX_CLK LOC = "P20"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_RX_DV LOC = "T22"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_RX_ER LOC = "U20"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_TXD[0] LOC = "U10"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_TXD[1] LOC = "T10"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_TXD[2] LOC = "AB8"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_TXD[3] LOC = "AA8"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_TX_CLK LOC = "L20"  |  IOSTANDARD = "LVCMOS25";
NET Ethernet_Lite_TX_EN LOC = "T8"  |  IOSTANDARD = "LVCMOS25";
NET IIC_DVI_SCL LOC = "W13"  |  IOSTANDARD = "LVCMOS25";
NET IIC_DVI_SDA LOC = "AA4"  |  IOSTANDARD = "LVCMOS25";
NET IIC_EEPROM_SCL LOC = "T21"  |  IOSTANDARD = "LVCMOS25";
NET IIC_EEPROM_SDA LOC = "R22"  |  IOSTANDARD = "LVCMOS25";
NET IIC_SFP_SCL LOC = "E5"  |  IOSTANDARD = "LVCMOS25";
NET IIC_SFP_SDA LOC = "E6"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_4Bits_TRI_O[0] LOC = "D17"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_4Bits_TRI_O[1] LOC = "AB4"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_4Bits_TRI_O[2] LOC = "D21"  |  IOSTANDARD = "LVCMOS25";
NET LEDs_4Bits_TRI_O[3] LOC = "W15"  |  IOSTANDARD = "LVCMOS25";
NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3"  |  IOSTANDARD = "LVCMOS25";
NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6"  |  IOSTANDARD = "LVCMOS25";
NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5"  |  IOSTANDARD = "LVCMOS25";
NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1"  |  IOSTANDARD = "LVCMOS25";
NET QSPI_FLASH_IO0 LOC = "AB20"  |  IOSTANDARD = "LVCMOS25";
NET QSPI_FLASH_IO1 LOC = "AA20"  |  IOSTANDARD = "LVCMOS25";
NET QSPI_FLASH_SCLK LOC = "Y20"  |  IOSTANDARD = "LVCMOS25";
NET QSPI_FLASH_SS LOC = "AA3"  |  IOSTANDARD = "LVCMOS25";
NET RESET LOC = "H8"  |  IOSTANDARD = "LVCMOS15"  |  TIG;
NET RS232_Uart_1_sin LOC = "H17"  |  IOSTANDARD = "LVCMOS25";
NET RS232_Uart_1_sout LOC = "B21"  |  IOSTANDARD = "LVCMOS25";
NET SysACE_CEN LOC = "W4"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_CLK LOC = "N19"  |  IOSTANDARD = "LVCMOS25";
NET SysACE_MPA[0] LOC = "V5"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPA[1] LOC = "V3"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPA[2] LOC = "P5"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPA[3] LOC = "P4"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPA[4] LOC = "H4"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPA[5] LOC = "G4"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPA[6] LOC = "D2"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[0] LOC = "N6"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[1] LOC = "N7"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[2] LOC = "U4"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[3] LOC = "T4"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[4] LOC = "P6"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[5] LOC = "P7"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[6] LOC = "T3"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPD[7] LOC = "R4"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_MPIRQ LOC = "AA2"  |  IOSTANDARD = "LVCMOS15"  |  TIG;
NET SysACE_OEN LOC = "T6"  |  IOSTANDARD = "LVCMOS15";
NET SysACE_WEN LOC = "T5"  |  IOSTANDARD = "LVCMOS15";
#
# additional constraints
#

NET "CLK" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
#
#
# PERSTN (input) signal.  The perstn signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a perstn reset signal is usually
# present on the connector.  For cable based form factors, a
# perstn signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#

NET "PCIe_perstn" TIG;
NET "PCIe_perstn" LOC = J7 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;
#
NET "*/REFCLK" TNM_NET = PCIe_Diff_Clk_TNM;
# 125MHz refclk:
TIMESPEC TS_PCIe_Diff_Clk = PERIOD PCIe_Diff_Clk_TNM 125000 kHz;
# 100MHz refclk:
# TIMESPEC TS_PCIe_Diff_Clk = PERIOD PCIe_Diff_Clk_TNM 100000 kHz;

NET "*axi_aclk_out*" TNM_NET = axi_aclk_out_TNM;
# 125MHz refclk:
TIMESPEC TS_axi_aclk_out = PERIOD axi_aclk_out_TNM TS_PCIe_Diff_Clk/2.0 HIGH 50 % PRIORITY 1;
# 100MHz refclk:
# TIMESPEC TS_axi_aclk_out = PERIOD axi_aclk_out_TNM TS_PCIe_Diff_Clk/1.6 HIGH 50 % PRIORITY 1;


#
# Transceiver instance placement.  This constraint selects the
# transceiver to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Spartan-6 GTP Transceiver User Guide for more
# information.
#
# PCIe Lane 0


NET  PCIe_Diff_Clk_N LOC = B10;
NET  PCIe_Diff_Clk_P LOC = A10;

INST */gtpa1_dual_i LOC = GTPA1_DUAL_X0Y0;
NET   PCI_Express_pci_exp_txp  LOC = B6;
NET   PCI_Express_pci_exp_txn  LOC = A6;
NET   PCI_Express_pci_exp_rxp  LOC = D7;
NET   PCI_Express_pci_exp_rxn  LOC = C7;

XMD%
XMD% fpga -f mblaze_0_top.bit
Fpga Programming Progress ......10....20....30....40....50....60...70....80....90.....Done
Successfully downloaded bit file.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       0a001093           8        System_ACE_CF
 2       34028093           6        XC6SLX45T

0
XMD% connect mb mdm

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       0a001093           8        System_ACE_CF
 2       34028093           6        XC6SLX45T

MicroBlaze Processor Configuration :
-------------------------------------
Version............................8.20.b
Optimization.......................Performance
Interconnect.......................AXI-LE
MMU Type...........................No_MMU
No of PC Breakpoints...............1
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........on
Instruction Cache Base Address.....0xc0000000
Instruction Cache High Address.....0xc7ffffff
Data Cache Support.................on
Data Cache Base Address............0xc0000000
Data Cache High Address............0xc7ffffff
Exceptions  Support................off
FPU  Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............on
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Data Cache Write-back Support......off
Fault Tolerance Support............off
Stack Protection Support...........off
ERROR: MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and its Bus Interfaces are connected properly
        UNABLE to STOP MicroBlaze

XMD% exit

[lobe]

Note!!!,

This Example when built under 13.4 also wont allow the Mblaze to come out of RESET.

So this seems to be a generic issue with 13.4

Laurence

[lobe]

I meant to add that if I use the BSB and the PLB bus this problem is not there. Seems to be specific to AXI

Laurence

[lobe]

Hello,

Using the BSB and leaving out everything connected to CF and SPI flash allowed me to build an AXI design with PCIE support.

This appears to be a known issue listed as a bug with the SP605, CF and PCIE when AXI is involved.

The SP605 shows up now with the BAR address enabled in my Linux system. I developed a Linux driver to mmap the memory.

Now I need help in understanding the address translation for the MIcroblaze and the AXI to BAR access.

I am able to send data from my Linux host but my code running on the Microblaze is not seeing the memory being updated.

I have to 64KB BAR registers in my EDK xml, one is PCIE, the other is AXI. I assume if I read from the PCIE address this should get me to the data being sent by the host.

I have been trying for over 6 months to get a Microblaze to communicate with the host over PCIE.

Thanks for any ideas.

[luisb]

Have you looked at the address translation section in the Datasheet? There are figures there to help explain this.

[lobe]

Hello, I did but I could not make it work.

I will admit I am new to this so probabay I am just doing something wrong.

I do have a webcase into Xilinx, but its been there for days and nobody has responded. It is really important for me to be able to run Linux on the SP605 for a proof of concept diagnostic tool.

So I need both CF and PCIE support with Microblaze.

I work for HP, so I though Xilinx would have wanted to help me with this. We are a huge Xilinx customer.

Thanks

Laurence

[lobe · Accepted solution]

The issue with RESET turned out to be a PCIE slot problem.
It works now so now I am in debugging the Linux kernel bring up.