05-25-2012 07:31 AM
Is there any kind of Cycle Accurate Model (in any form, C/HDL/crypted code/Synopsys model...what ever) for
PS part of Zynq device? (or even some sections of it. )
( from Xilinx , ARM or any other company...)
05-25-2012 07:52 AM
If you buy the ARM license, then I am sure you will be able to have that.......
But, what you ask is the question asked by many who desire to make their own SoC.
In the book that I co-authored "FPGA Prototyping Methodology Manual" with Doug Amos and Rene Richter of Synopsys, examines this, and other issues.
Basically, a cycle accurate model of something this complex, is either the RTL for it, or a model written in c that matches the RTL (which is really hard). Neither the RTL, nor the c code for this is free, and both belong to ARM. So, if you are on that path, then you will need to obtain the licenses from those IP suppliers.
Xilinx San Jose
05-25-2012 08:28 AM
Thanks for the description,
Here another question comes into my mind:
How much of the architecture in PS part of Zynq is really by ARM? Did Xilinx do any modification to the architecture to adapt it to the rest of the Zynq system?
For example, we can say, the MPCores are completely from ARM, and so, if you obtain a model for them from ARM the numbers also hold through for Zynq PS part, but, what if I was doing transactions to OCM?
or even I am wondering if the SCU and L2 are exactly as those used in pure ARM based designs?
05-25-2012 08:53 AM
The Zynq system licensing agreements are proprietary.
I am unable to comment on the parts that we did, and the parts that ARM is responsible for.
For that information, I suggest you make the request to your local Xilinx sales office.
Obviously, the AXI4 bus is new, and was jointly developed by ARM and Xilinx, so that one is pretty easy to guess at based on press releases, etc. And, the 5-way AXI4 bus switch in the PS subsystem, and the means by which is communicates to the FPGA fabric, is also obviously Xilinx (and the reason why it is so powerful and so useful, as opposed to an ARM just 'bolted' onto a FPGA).
It took more than 5 years to optimize the architecture and design of this product, so anyone claiming "me too!" is likely to mess things up pretty badly (it takes a while to examine, and optimize such a complex system!).
Xilinx San Jose