Embedded Processors and Peripherals

[glenn.ramsey]

Hi. I have a project that uses the ppc440mc_ddr2 core to connect the powerpc to an external DDR2 component. Unfortunately, I am getting odd addressing issues where a single write will write to multiple memory locations. In attempting to debug this, I have found that going through the MIG will allow me to access a debug port giving me full access to the physical signals and even allow me to dynamically adjust IDELAY tap values, which is amazing. However, MIG does not generate a design that can be directly interfaced with the powerpc like the ppc440mc_ddr2 core. Searching through the documentation on the core, there appears to be no option to generate a debug port on the ppc440mc_ddr2 core and the DDR2 signals can not simply be connected to a Chipscope core.

I was wondering if anybody knew of a better way to go about debugging the DDR2 connection besides attempting to glue the output from the MIG to the powerpc.

Regards,

Glenn 

[pdabrowski]

Hey Glenn -- Did you ever manage to hack the debug port in into the ppc440mc_ddr2 core? I'm also trying to get a little more information while debugging this IP core. Thanks!

-Paul

[glenn.ramsey]

Hi Paul. Fortunately for me I realized I was running the DDR2 at too slow of a clock speed. Speeding it up solved my problem, so I never delved into hacking the debug port out of the IP. Best of luck!

[bmjeffer@rockwellcollins.com]

I'm curious about this as well. Any update on whether it is possible?

I'm having trouble getting the PPC to communicate with the memory and am wondering if its stuck in the initialization sequence somewhere. I've also not had any luck getting chipscope hooked up to monitor the DDR2 signals. Any suggestions?

Thanks,

bryan

[dylan]

Working with multiple designs with issues like this, theres a few things to look at.

First sure all of the MIG-related UCF and MHS constraints are correct.  See a 11.2 or later datasheet, as I've rewritten the how-to sections of that correct. If you've changed your pinout, a new MIG UCF and potentially MHS parameter is necessary.

Pay special attention to the PPC440 CPU MHS parameters, as they depend on the memory controller settings.  C_PPC440MC_CONTROL, C_BANK_CONFLICT, C_ROW_CONFLICT are the important ones.  These will have new DRCs to generate error messages for poor choices in 12.1 and 12.2.

If still in v2, check the various *_BITS MHS parameters.  They need to match the various *_WIDTH parameters exactly, or things won't work. These are handled automatically in v3.00.a and later.

Check clock frequencies and the rest of the memory controller timing values.

Upgrade to v3.00.a in 11.4.

You've likely solved your problem by now. But if you've checked and double-checked the UCF and MHS parameters and suspect a memory interface problem, consider creating a MIG design to debug the physical parts of the interface, since there is more intrumentation that can be used.

[bmjeffer@rockwellcollins.com]

Thanks for the response. Which file are you referring to?

I went through ppc440mc_ddr2.pdf and setup those three constants according. However, that didn't seem to solve my problem. I'm sure my UCF is correct, not so confident in the MHS. (I've included the PPC440 and DDR2 blocks below)

I have not been able to generate a bitfile that has a chipscope module that monitors the DDR2 signals and I don't see any options for enabling debug ports on the ppc440mc. Any suggestions there? Is it possible to easily chipscope signals internal to the MC?

bryan

BEGIN ppc440_virtex5

PARAMETER INSTANCE = ppc440_0

PARAMETER C_IDCR_BASEADDR = 0b0000000000

PARAMETER C_IDCR_HIGHADDR = 0b0011111111

PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0

PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0

PARAMETER HW_VER = 1.01.a

PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x001FFF80

PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x0E000000

PARAMETER C_PPC440MC_CONTROL = 0xF8D0008F

BUS_INTERFACE MPLB = plb_v46_0

BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus

BUS_INTERFACE RESETPPC = ppc_reset_bus

BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC

PORT CPMC440CLK = clk_400_0000MHzPLL0

PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0

PORT CPMINTERCONNECTCLKNTO1 = net_vcc

PORT CPMMCCLK = clk_200_0000MHzPLL0_ADJUST

END

BEGIN ppc440mc_ddr2

PARAMETER INSTANCE = ddr2

PARAMETER HW_VER = 3.00.a

PARAMETER C_DDR_DWIDTH = 16

PARAMETER C_DDR_RAWIDTH = 13

PARAMETER C_DDR_BAWIDTH = 3

PARAMETER C_MEM_BASEADDR = 0x00000000

PARAMETER C_MEM_HIGHADDR = 0x07FFFFFF

PARAMETER C_DDR2_ODT_SETTING = 0

BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC

PORT DDR2_DQ = DDR2_DQ

PORT DDR2_DQS = DDR2_DQS

PORT DDR2_DQS_N = DDR2_DQS_n

PORT DDR2_A = DDR2_Addr

PORT DDR2_BA = DDR2_BankAddr

PORT DDR2_RAS_N = DDR2_RAS_n

PORT DDR2_CAS_N = DDR2_CAS_n

PORT DDR2_WE_N = DDR2_WE_n

PORT DDR2_CS_N = DDR2_CS_n

PORT DDR2_ODT = DDR2_ODT

PORT DDR2_CKE = DDR2_CE

PORT DDR2_DM = DDR2_DM

PORT DDR2_CK = DDR2_Clk

PORT DDR2_CK_N = DDR2_Clk_n

PORT idelay_ctrl_rdy_i = net_vcc

PORT mc_mibclk = clk_200_0000MHzPLL0_ADJUST

PORT mi_mcclk90 = clk_200_0000MHzPLL0

PORT mi_mcclkdiv2 = clk_100_0000MHzPLL0_ADJUST

PORT mi_mcclk_200 = clk_200_0000MHzPLL0_ADJUST

PORT mi_mcreset = sys_bus_reset

END

[dylan]

Since the default CA_WIDTH is 10, I get:

PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x000FFF80

PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00700000

[bmjeffer@rockwellcollins.com]

Thanks dylan. I agree with your numbers and see where I went wrong in my calculations. However, that still doesn't fix my problem.

I've noticed that I lose debug control of the PPC through XMD after trying a DDR2 memory access. I do a "rrd" in XMD and see that all registers have 0xF7FFEFEF, which is the same value that XMD reports for every DDR2 address I try to read. Any ideas?

bryan

[dylan]

Is your memory clock and memory clock 90 phase aligned?

How are you sure that your UCF is OK?  What process did you follow to obtain it? Were any pins changed for layout purposes?

[bmjeffer@rockwellcollins.com]

Hi dylan,

I did find a problem in the clock being used. I opened the clock block in xps and it found it automatically and corrected. That seemed to have improved things some, but I'm still not all the way there. Now, in XMD I do not lose registers after attempting ddr2 writes and doing a "rrd" shows that they are still ok. However, after doing a write I do a ddr2 read and I see the data I just tried to write being reported in every address. I've scoped the signals on the board going to the memory and they don't appear to be toggling for a write/read, so it must be reporting something left over on the plb.

When I scope the signals I see CS_L low for all time, WE_L toggles low every period, CAS_L toggles low every period, RAS_L toggles low a few times (3) every period. The ODT signal is low for all time. A period is 7.8us.

I went through MIG to generate the ucf. I then modified it according to "Using Custom MIG-Compatible Pinouts" section of ppc440mc_ddr2.pdf, except for steps 6 and 7. I tried setting those parameters in the mhs, but it errored out in xps. No pins were moved and I've used the defaults that MIG suggested.

Thanks again for the help. I feel like I'm getting a little closer.

-bryan