Embedded Processors and Peripherals

[codewarrior1241]

Hi all,

I'm trying to synthesize a system using the AXI Virtual FIFO Controller 1.00a. There is no information on it anywhere, nor is there a datasheet... I make it through the DRC of the XPS tool fine, but when running PlatGen, I get the following error when the tools get to synthesizing the FIFO controller. I shortened the list of MPD constants slightly for brevity:

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <system_axi_vfifo_ctrl_0_wrapper>.
    Related source file is "L:\Personal\Vadim\Boonton\ZynqDemoBoard\r.Builds\_Working\d.Zynq\e.XPS\hdl\system_axi_vfifo_ctrl_0_wrapper.vhd".
    Summary:
	no macro.
Unit <system_axi_vfifo_ctrl_0_wrapper> synthesized.

Synthesizing Unit <axi_vfifo_ctrl>.
    Related source file is "C:/Xilinx/ZynqBeta21/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_vfifo_ctrl_v1_00_a/hdl/vhdl/axi_vfifo_ctrl.vhd".
        C_FAMILY = "zynq"
        C_DRAM_BASE_ADDR = "80000000"
        ...
        C_NUM_PAGE_CH5 = 8
        C_NUM_PAGE_CH6 = 8
       ...
        C_AR_WEIGHT_CH7 = 8
    Set property "GENERATOR_DEFAULT = generatecore com.xilinx.ip.axi_vfifo_ctrl_v1_1.axi_vfifo_ctrl_v1_1" for instance <vfifo_inst>.
    Summary:
	no macro.
Unit <axi_vfifo_ctrl> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================
Overriding Xilinx file <arwz> with local file
<C:/Xilinx/ZynqBeta21/ISE_DS/ISE/bin/nt64/arwz.exe>
Release 14.1 - generatecore $Revision: 1.68 $ (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
WARNING:coreutil:1006 - Xilinx repository path
   'C:\Xilinx\ZynqBeta21\ISE_DS\EDK\coregen' is not a valid directory
WARNING:encore:391 - Could not identify root family of 'zynq'.
INFO:encore:403 - Generating cell
   'system_axi_vfifo_ctrl_0_wrapper_axi_vfifo_ctrl_v1_1' of component
   'system_axi_vfifo_ctrl_0_wrapper_axi_vfifo_ctrl_v1_1' using IPEngine
   generatecore flow.
ERROR:coreutil:607 - Cannot set immediate value
ERROR:coreutil:814 - Error setting value of parameter 'c_ar_weight_ch5'.
ERROR:encore:368 - Could not set model parameter 'C_AR_WEIGHT_CH5' to value '8'
ERROR:encore:394 - Could not set SIM parameters on IP 'AXI Virtual FIFO
   Controller v1.1'
ERROR:encore:402 - Failed to generate unit
   'system_axi_vfifo_ctrl_0_wrapper_axi_vfifo_ctrl_v1_1'.

 Why is it not finding a macro for this peripheral?