Yep, we're having problems as well and are about to give up on FSL unless someone can figure out why we are seeing the glitches we are seeing. We are using the FSL bus to communicate back and forth with a custom component as well. We use the control bit to indicate address. Control bit = 1 is address, control = 0 is data. Quite often the data and addresses coming up are wrong. There is logic in our custom component to increment the address of each new integer of data until it sees another address (control = 1). Look below, the problem we are currently seeing is that fairly often the Exists bit goes high before the data is ready or the control bit goes high, so we read garbage. Then the exists bit doesn't go high again during the period where the data is valid so we miss the good data (in this case an address, kind of important :)). Any ideas? Would going back to version c help? We've been on D the whole time as far as I know so I don't know if it works on C yet. We'll try that before we give up and switch to a PLB implementation.
