07-22-2012 02:23 PM
I am using the Multi-Port Memory Controller (mpmc) v6.05.a in a design for a custom Virtex-4 board. I an using a custom NPI interface for writing data to the memory.
Data is in most cases written with 64-word burst transfers: First it is written to the Write FIFO, and then the burst write is requested.
While the Write FIFO is being filled, the design can run into a state where it is neceasary to reset the FIFO to the empty state without actually writing the data to memory. There is an input PIM<Port_Num>_WrFIFO_Flush, but according to the data sheet it is "Reserved".
Is there any way to safely flush the FIFO? The data sheet does not seem to contain any information on this topic.
For now, I only see the following way:
Request a 64-word burst transfer to an otherwise unused address. (The data queued in the FIFO should be less than or exactly 64 words.)
Wait for PIM<Port_Num>_WrFIFO_Empty to be asserted.
Wait for another 32 clock cycles before queuing new data, since the actual write transfer may have started when the PIM<Port_Num>_WrFIFO_Empty was asserted, and data queued during the transfer might be written out with the burst.
The question here is: Is it legal to request a 64 word burst transfer when fewer than 64 words might be in the FIFO?
07-22-2012 09:20 PM
Correct, the write flush is not supported.
Your overall method of aborting data to an unused area should work.
However, I'd recommend reading the "Restrictions on Block RAM FIFOs" section of the MPMC datasheet (unless you are using SRL FIFOs). Note that up to 1024 bytes of data can be written into the fifos. So as long as your controller does not push more that 4 full-size bursts at a time, you will be OK.
It is legal to request a burst before all of the data is in the write fifo. However, you must ensure that the FIFO does not underflow, as there is no protection from it. You can guarantee this due to the clock/data width ratios of the memory controller to the NPI interface/DDR DQ width. See the same section for this.