Embedded Processors and Peripherals

[roketroket]

I cleared project but the problem continues, can this be a problem of ISE version 14.1?

Anyone managed to connect multiple BRAMS to instruction bus in 14.1 and generate programing file with no errors?

[thirdeye]

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roketroket wrote:

I cleared project but the problem continues, can this be a problem of ISE version 14.1?

Anyone managed to connect multiple BRAMS to instruction bus in 14.1 and generate programing file with no errors?

---

I am not sure I ever got it to work connected ot the instruction bus.

I ended up attaching the extra BRAMs to the AXI after a not-so-useful webcase and getting sick of trying to make it work.

I was told that shoud work, but I am not sure I ever got it to.

The AXI ones definitely work for me in 13.4

Josh

[youngn11]

Hello.  I am running into the exact same issue as roketroket.

I have an ISE14.1 based design with .xmp core created by XPS.  I need to increase the (contiguous) base memory of the Microblaze from 64K to 128K.

Just as roketroket did - I have added an addition block ram and instruction/data controllers to the LMB, and assigned one controller to address 0x00000000 to 0x0000FFFF, and the 2nd controller from 0x00010000 to 0x0001FFFF.

XPS DRC passes ok, and it generates a netlist successfully.

However, when I rebuild the ISE design to use the new Microblaze core, error messages occur.

Specifically, synthesis and Place/Route  pass ok, but after running bitgen in the 'generate programming file' portion, 16 similar error messages are created.

(example of 4 of these error messages follows):

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f top.ut top.ncd

ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<0>> is incomplete. The
   signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<2>> is incomplete. The
   signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<3>> is incomplete. The
   signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<4>> is incomplete. The
   signal is not driven by any source pin in the design.

I have cleaned both the XPS project and the ISE project., regenerated netlist in XPS, and attempted to rebuild the entire ISE design.  Unfortunately, the error(s) persist.

[thirdeye]

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youngn11 wrote:

Hello.  I am running into the exact same issue as roketroket.

I have an ISE14.1 based design with .xmp core created by XPS.  I need to increase the (contiguous) base memory of the Microblaze from 64K to 128K.

Just as roketroket did - I have added an addition block ram and instruction/data controllers to the LMB, and assigned one controller to address 0x00000000 to 0x0000FFFF, and the 2nd controller from 0x00010000 to 0x0001FFFF.

XPS DRC passes ok, and it generates a netlist successfully.

However, when I rebuild the ISE design to use the new Microblaze core, error messages occur.

Specifically, synthesis and Place/Route  pass ok, but after running bitgen in the 'generate programming file' portion, 16 similar error messages are created.

(example of 4 of these error messages follows):

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f top.ut top.ncd

ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<0>> is incomplete. The
   signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<2>> is incomplete. The
   signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<3>> is incomplete. The
   signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:368 - The signal
   <cpu1/microblaze_0_i_bram_ctrl2_BRAM_PORT_BRAM_Addr<4>> is incomplete. The
   signal is not driven by any source pin in the design.

I have cleaned both the XPS project and the ISE project., regenerated netlist in XPS, and attempted to rebuild the entire ISE design.  Unfortunately, the error(s) persist.

---

I saw the same issue in 13.4 adn ended up putting 128K BRAMs on the AXI bus instead of the LMB bus. I then made the LMB bus BRAMs 8K or something since not as many were needed.

The linker script makes it "easy" to put different sections of the program into differnt memories.

My .text and .data sections tend to be large while other sections tend to be small.

I will sometimes put most code sections into the LMB BRAMs adn then add a separate AXI BRAM block or two to house the larger sections.

I believe there is no problem with placing the AXI BRAM address space adjacent to the LMB address space and calling them one even though on different busses, but I could be wrong about that.

Happy debugging!

Try the AXI though - I bet it will work first try - it did for me.

Josh

[youngn11]

Thanks.  I will give the AXI attached BRAMs a try. 

Do you know if the bitstream tools are able to download code to the AXI attached BRAMs directly via the download.bit file?  (It seems like they should be able to be initialized with code).  Or, like external memory, do they need to be loaded using a bootloader and download utility like XMD/dow ?

[thirdeye]

Yes, if the linker script directs the sections of code to the BRAMs then they will be initialized in the bitstream.

This will work regardless of whether they are attached to the AXI or the LMB interface.

This is the whole advantage of using BRAMs instead of DDR for me.

Josh

[hamze]

In  ISE 14.1 do right-click on "generate programming file"

then choose "Process properties" and then "general option"

then uncheck first line ( DRC)

rerun generate program file

you will not see these errors

It seems that this option is turned on in version 14.1 while it was not in ISE 13.3

[dawatson]

Has anyone managed to attach more BRAM controllers to the LMB whilst using an AXI system? I could do this using the PLB but everytime I've tried it when using AXI I get a load of timing errors. I know you can ignore them but I'd rather have a correct implementation rather than something that could break.

[thirdeye]

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dawatson wrote:

Has anyone managed to attach more BRAM controllers to the LMB whilst using an AXI system? I could do this using the PLB but everytime I've tried it when using AXI I get a load of timing errors. I know you can ignore them but I'd rather have a correct implementation rather than something that could break.

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I thought I had finally gotten them working for me attached to the AXI, but now I am not sure I ever did get it free of errors, let alone warnings. Sorry, but I am just not sure.

Xilinx told me it should work in a webcase.

They suggested using the AXI rather than the LMB connections to add additional BRAMs.

Josh

[dawatson]

I've managed to get rid of the timing errors by exporting to SDK through ISE. You can choose different placement options to try get rid of the timing errors, think the XPS must use the default (balanced) option which doesn't help!