Embedded Processors and Peripherals

[thobmei]

Hi

im trying do RESET my IPIF(attached to the PLB BUS)

FIFO via the SMALFIFO_mReset(XPAR_SMALFIFO_0_BASEADDR); funktion but it seems to Fail.The READ Fifo stays Empty ....

And I cant figure out why.

After the RESET the Applicatcion should start Counting in the Fifo ...

the std_logic Signal RTP (RESET TOOK PLACE) indicates the Start.....

I Modified the Default Template in this way:

 case fifo_cntl_cs is
      when IDLE =>
        -- data is available in the write fifo and there's space in the read fifo,
        -- so we can start transfering the data from write fifo to read fifo
        if (RFIFO2IP_full = '0' and RTP='1') then
          fifo_cntl_ns   <= RD_REQ;
        end if;
      when RD_REQ =>
        -- data has been read from the write fifo,
        -- so we can write it to the read fifo
        if ( WFIFO2IP_RdAck = '1' ) then
          --DATA <= DATA +1;
          fifo_wrreq_cmb <= '1';
          fifo_cntl_ns   <= WR_REQ;
        end if;
      when WR_REQ =>
        -- data has been written to the read fifo,
        -- so data transfer is done
        if ( RFIFO2IP_WrAck = '1' ) then
          fifo_cntl_ns <= IDLE;
        end if;
      when others =>
        fifo_cntl_ns <= IDLE;
    end case;

  end process FIFO_CNTL_SM_COMB;

  FIFO_CNTL_SM_SEQ : process( Bus2IP_Clk ) is
  begin

    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
      if ( Bus2IP_Reset = '1' ) then
        IP2WFIFO_RdReq <= '0';
        IP2RFIFO_WrReq <= '0';
        DATA_temp <= (others => '0');
        RTP <= '1';
        fifo_cntl_cs   <= IDLE;
      else
        IP2WFIFO_RdReq <= fifo_rdreq_cmb;
        IP2RFIFO_WrReq <= fifo_wrreq_cmb;
        DATA_temp <= DATA_temp +1;
        fifo_cntl_cs   <= fifo_cntl_ns;
      end if;
    end if;

  end process FIFO_CNTL_SM_SEQ;

  IP2RFIFO_Data <= DATA_temp;

Thanks 4 your time ....

Tobias

[thobmei]

Ive tested the IpIF with modelsim and it starts working after the bus2ip_reset.

Thats my software:

// Code for FIFIMDAINT_DMA1


#include "xstatus.h"
//include "xintc_l.h"
//#include "xdmacentral_l.h"
//#include "xdmacentral.h"
#include "xparameters.h"
#include "smalfifo.h"
#include "xenv_standalone.h"

//-- added for xio functions
#include "xutil.h"
#include "xio.h"

//#define SIMPLEFIFO_baseaddr 0xCC600000//XPAR_SIMPLEFIFO_0_BASEADDR;

int main (){


   // ---- Test FIFODMAINT ----------------
   //
   // Write to the Write Packet FIFO and read back from the Read Packet FIFO
   //
   xil_printf("Packet FIFO test...1A\n\r");
   xil_printf("   - reset write packet FIFO to initial state\n\r");
   
   //SMALFIFO_mReset(XPAR_SMALFIFO_0_BASEADDR);
   //SMALFIFO_mResetWriteFIFO(XPAR_SMALFIFO_0_BASEADDR);
   //xil_printf("   - reset read packet FIFO to initial state \n\r");
   //SMALFIFO_mResetReadFIFO(XPAR_SMALFIFO_0_BASEADDR);
   SMALFIFO_mReset(XPAR_SMALFIFO_0_BASEADDR);
   //xil_printf("   - push data to write packet FIFO\n\r");
   int Index;
   /*for ( Index = 0; Index < 10; Index++ )
   {
      xil_printf("     0x%x", Index*1+1);
      SMALFIFO_mWriteToFIFO(XPAR_SMALFIFO_0_BASEADDR, 0, Index*1+1);
      xil_printf("\n\r");
    }*/
   xil_printf("   - write packet FIFO is %s\n\r", ( SMALFIFO_mWriteFIFOFull(XPAR_SMALFIFO_0_BASEADDR) ? "full" : "not full" ));
// ------------- next step looking at reading written value back and displaying ------------------
  /*
   * FIFO example in user logic will loop WrFIFO data back to RdFIFO,
   * so we get number of entries from RdFIFO instead of WrFIFO.
   * Reg32Value = SMALFIFO_mWriteFIFOVacancy(baseaddr);
   */
   u32 Reg32Value;
   Reg32Value = SMALFIFO_mReadFIFOOccupancy(XPAR_SMALFIFO_0_BASEADDR);
   xil_printf("   - number of entries is %d\n\r", Reg32Value);
   xil_printf("   - pop data out from read packet FIFO\n\r");
   for ( Index = 0; Index < 10; Index++ )
   {
    Reg32Value = SMALFIFO_mReadFromFIFO(XPAR_SMALFIFO_0_BASEADDR, 0);
    xil_printf("    %d", Reg32Value);
    /*if ( Reg32Value != (Xuint32) Index*1+1 )
    {
      xil_printf("\n\r");
      xil_printf("   - unexpected value read from read packet FIFO\n\r");
      xil_printf("   - write/read packet FIFO failed\n\r");
      //SMALFIFO_mResetWriteFIFO(XPAR_SMALFIFO_0_BASEADDR);
      //SMALFIFO_mResetReadFIFO(XPAR_SMALFIFO_0_BASEADDR);
      return XST_FAILURE;
    }*/
    xil_printf("\n\r");
   } // End for loop
   
   
   
   xil_printf("   - read packet FIFO is %s\n\r", ( SMALFIFO_mReadFIFOEmpty(XPAR_SMALFIFO_0_BASEADDR) ? "empty" : "not empty" ));
   Reg32Value = SMALFIFO_mReadFIFOOccupancy(XPAR_SMALFIFO_0_BASEADDR);
   xil_printf("   - number of entries is %s %d \n\r", ( Reg32Value == (Xuint32) 0 ? "expected" : "unexpected" ), Reg32Value);
   SMALFIFO_mResetWriteFIFO(XPAR_SMALFIFO_0_BASEADDR);
   SMALFIFO_mResetReadFIFO(XPAR_SMALFIFO_0_BASEADDR);
   xil_printf("   - write/read packet FIFO passed \n\n\r");



return 0;
}

The Output is:

Packet FIFO test...1A
   - reset write packet FIFO to initial state
   - write packet FIFO is not full
   - number of entries is 0
   - pop data out from read packet FIFO
    844300287
    844300287
    844300287
    844300287
    844300287
    844300287
    844300287
    844300287
    844300287
    844300287
   - read packet FIFO is empty
   - number of entries is expected 0
   - write/read packet FIFO passed

So It seems that I dont get any Values from the ipif

proc_sys_reset is Preset:

 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 2.00.a (...)

[thobmei]

in MHS

It looks that way:

BEGIN smalfifo
 PARAMETER INSTANCE = smalfifo_0
 PARAMETER HW_VER = 1.04.a
 BUS_INTERFACE SPLB = mb_plb
END

Is the RESET connected?

Acording to the Wizzard the RESET of the ipif is connected in the Right way to the plb....

[thobmei · Accepted solution]

Oo I found an mistake in my sensetivity list ...