Embedded Processors and Peripherals

[rabbitwayne]

Hey,

I am now working on the OpenSPARC EDK project. It takes 1 hour to generate the bitstream on my machine everytime I modify the project. I added some peripherals to the system. I wonder are there any other users of the OpenSPARC EDK project, and how much time it takes for you to generate the bitstream?

My current computer has an i7 processor with 2.8GHz frequency and 4GB memory. Now I want to buy a new computer or workstation to shorten this time as much as possible. I wonder what are the bottlenecks of the synthesis time. Higher CPU frequency, more memory, and anything more? Has anybody ever tried to upgrade machine to shorten the synthesis time?

Thanks a lot!

Wayne

[evgenis1]

Hi Wayne,

One hour build time might not be that bad. It can easily take several hours to build a large design running at high frequency. 

There is a long list of things to try to improve build time, including:

   more memory

   faster hard drive

   running on a Linux machine (it's faster than Windows)

   enabling multi-threaded MAP and PAR (-mt option)

   floorplanning (better consistency)

   partitions

   experimenting with tool options (e.g. reducing effort level)

What's the FPGA you're using, clock speeds, and design size ? 

Thanks,

Evgeni

[gszakacs]

Better performance in ISE tools generally goes with CPU speed, Size of cache, front-side bus speed,

and memory size pretty much in that order.  Note that number of CPU's is only somewhat helpful as

many of the longest processes are not currently parallelizable.

As far as system memory, this will determine how large of a project (i.e. can you fill a 330K LUT part)

and how many instances of the tools you can run in parallel (useful for SmartXplorer).  If you

want to use more than 2G of memory, you should go with a 64-bit operating system.  Note that

adding more memory will not help if your project does not cause the system to page to the disk.

Cache memory is a huge win in processing time.  Avoiding the memory access time to go through

the front-side bus to RAM allows the process to run many times faster.  Look for the processor chip

with the most cache available to any one CPU, since more cache that is not available to the

one you're using is no help.

-- Gabor

[rabbitwayne]

Hi Evgeni,

Thanks very much for your answer!

The FPGA board I use is ML505 XUP board and the FPGA chip is XC5VLX110T. There are multiple clocks in the design. The fastest clock may be up to 200MHz. The design takes almost 90% of all the resources available on the FPGA chip.

You mentioned about "enabling multi-threaded MAP and PAR (-mt option)", I wonder how to set this in EDK.

Thanks very much!

Best,

Wayne

[rabbitwayne]

Hi Gabor,

Thanks very much for your answer!

Another question. If I already have a machnine, what measures can I still take to improve the performance of the ISE tools?

Thanks,

Wayne