Embedded Processors and Peripherals

[andrewsi]

I'm using a Nexys-3 dev board which has an AXI4LITE IP that handles the fact that the onboard flash and PSRAM chips share address and data lines with each other.

I was curious to try turning on caching on the Microblaze to improve performance when running apps out of the PSRAM (after being copied from flash by an SREC bootloader.)  If I do this and connect the DC and IC lines from the Microblaze to the AXI4LITE bus, I then get a pile of warnings from the EDK about having all my AXI4LITE peripherals connected to the AXI4 cache (basically, mismatch of the bus type).

Since there's no documentation of the warning in question (EDK:3877, I believe), I am curious whether:

a) Will this work at all? In other words, will the cache have any benefit without being hooked up via a full AXI4 bus, and

b) Is the warning benign or not?  (Will an AXI4 master deal gracefully with being attached via an AXI4LITE interconnect?)

Thanks-

Andy

[andrewsi · Accepted solution]

Think I answered my own question, both by reading the Microblaze ref guide, as well as experimentation.

1) The cache interface does seem to want a full AXI4 implementation to the memory it's caching.  So that pretty much seems to rule out being able to cache the Nexys-3's PSRAM unless Digilent decides to upgrade the memory mux IP to full AXI4 from AXI4LITE.

2) The proc crashes as soon as you enable the caches in the processor status register, on the off chance that you try it anyway. :-)