Embedded Processors and Peripherals

[smazzux]

Dear Xilinx community,

hello to everybody.

I am having problems in undertanding some strange behaviours of the RTC component of the axi ethernet ip (version 3.00.a - under ISE 13.4).

I was able to succesfully program positive and negative offsets by giving a negative second filed (like a signed integer - even if on the datasheet it is stated as being unsigned).
I noticed that if the nanosecond field wraps around during offset compensation the second field is not affected. Is this the intended behaviour?

Secondly and most important, I am noticing strange behaviours whilst reading the RTC value after issuing an RTC offset update.
Sometimes I read inconsistent values.
Some others it seems to be affected by previous upddates.
I could trigger some different behaviours if issuing an update with empty (0) values.
I am attaching a sample SDK code.

I also tried to clear interrupts (that I am not using, anyway) to no avail.
My only concern is about giving offset compensations and reading the current value.

Is anyone else using the RTC component out there? 

Can anyone provide additional information about some handling of the core that maybe is not stated in the datasheet, or just confirm the behaviour?

Many thanks and best regards.
Giulio

[smazzux]

In the end I ended up writing my own RTC module.

It is quite simple and only permits to read the current value and to program a step adjustment.

It also generates a PPS signal on the second boundary.

Since the fileds are 32 bits in length it is quite easy to issue a negative adjustment by just using the 2 complement of the wanted positive values (both for seconds and for nanoseconds).

Hopefully it will be useful to somebody else, too.

Best regards,

Giulio