Embedded Processors and Peripherals

[bassman59]

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skimura_lynx wrote:

So what is my best option for doing this? Just from reading the original post of this thread, I don't think I want to interface to mpmc via the PLB bus; seems like I would run into more latency/speed issues.

What is the "fastest" bus I can use to connect to mpmc, and how would I do this (ie VFBC or something)? Does Xilinx offer any help in designing modules to connect via these types of busses?

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Part of the latency is in the MPMC. Its delay is absurd. Since I have a requirement to capture real-time data at a somewhat ridiculous rate (I get two 8-bit words with every 240 MHz clock) I need a memory interface that can keep up, so I'm writing my own. It could be attached to the PLB (the other interfaces are not available on PPC) or be connected to a standalone DMA controller.

The Xilinx cores are useful as a proof-of-concept, but in general are very low performance. Your options are: high performance, low cost, immediate availablity for use in your design. Pick two.

-a

(I suppose "low cost" is a misnomer; if you have to write the code yourself, there is a cost involved. But most companies account for salaries separately from capital or other expensives, so if you don't have to write a check out to some IP company for their core, it's "low cost.")

[skimura_lynx]

Interesting. Your requirements are pretty ridiculous :smileysurprised: .

So correct me if I'm wrong, but you said that you were going to "write your own memory interface", but then talked about how you might attach it to the PLB bus. So are you just rewriting the top-most PLB layers of your modules to improve performance, or are you going to re-invent the wheel with your own custom bus protocol?

[bassman59]

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skimura_lynx wrote:

Interesting. Your requirements are pretty ridiculous :smileysurprised: .

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I find it's worthwhile knowing from the start that the requirements are ridiculous. Then there's no surprise!

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So correct me if I'm wrong, but you said that you were going to "write your own memory interface", but then talked about how you might attach it to the PLB bus. So are you just rewriting the top-most PLB layers of your modules to improve performance, or are you going to re-invent the wheel with your own custom bus protocol?

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I need a memory controller that doesn't suck. And there's no real reason why it couldn't be used as a memory controller for a processor, and attaching it to PLB directly (not going through the Xilinx wrappers) appears to be pretty straightforward. I am not re-inventing the wheel. Consider that PLB isn't all that different from any other processor bus: you decode an address and access type (read/write, burst/single), and handle the data phase.