Sign In

Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Visitor
engmoneer
Posts: 7
Registered: ‎04-27-2010
0

Xilinx mutex core dosn't support four PLB interface

Hello everybody

 

I designed a multi Microblaze processor system with four Microblaze processors using the board ML510. the four processors connects to each other with an FSL busses and share the same console "RS232" which is connected to the first processor "Microblaze_0" through its "PLB_0" bus. I used three PLBv46-to_PLBv46 bridge to connect the PLB_0 to the other three busses "PLB_1", "PLB_2" and "PLB_3" to let the remaining processors to see the adress of the perioheral "RS232". In order to synchronize the four processors I used the Xilinx mutex core with four SPLB port to connect the four PLB buses of the four processors.

 

The problem occured in the driver of the mutex core. The file xparameters.h for the first and second processors contains the definitions of the driver parameters of the mutex core, but the file xparameters.h for the third and fourth processors don't have.

 

1. xparameters.h for microblaze_0 wich connected to PLB_0

/* Definitions for peripheral XPS_MUTEX_0 */
#define XPAR_XPS_MUTEX_0_IF_0_DEVICE_ID 0
#define XPAR_XPS_MUTEX_0_TESTAPP_ID 0
#define XPAR_XPS_MUTEX_0_IF_0_BASEADDR 0x82400000
#define XPAR_XPS_MUTEX_0_IF_0_NUM_MUTEX 16
#define XPAR_XPS_MUTEX_0_IF_0_ENABLE_USER 0
#define XPAR_XMUTEX_NUM_INSTANCES 1
 
/******************************************************************/
 
 
/* Canonical definitions for peripheral XPS_MUTEX_0 IF 0 */
#define XPAR_MUTEX_0_DEVICE_ID XPAR_XPS_MUTEX_0_IF_0_DEVICE_ID
#define XPAR_MUTEX_0_BASEADDR 0x82400000
#define XPAR_MUTEX_0_HIGHADDR 0x8240FFFF
#define XPAR_MUTEX_0_NUM_MUTEX 16
#define XPAR_MUTEX_0_ENABLE_USER 0

2. xparameters.h for microblaze_1

 

/* Definitions for peripheral XPS_MUTEX_0 */
#define XPAR_XPS_MUTEX_0_IF_1_DEVICE_ID 0
#define XPAR_XPS_MUTEX_0_TESTAPP_ID 0
#define XPAR_XPS_MUTEX_0_IF_1_BASEADDR 0x82600000
#define XPAR_XPS_MUTEX_0_IF_1_NUM_MUTEX 16
#define XPAR_XPS_MUTEX_0_IF_1_ENABLE_USER 0
#define XPAR_XMUTEX_NUM_INSTANCES 1
 
/******************************************************************/
 
 
/* Canonical definitions for peripheral XPS_MUTEX_0 IF 1 */
#define XPAR_MUTEX_0_DEVICE_ID XPAR_XPS_MUTEX_0_IF_1_DEVICE_ID
#define XPAR_MUTEX_0_BASEADDR 0x82600000
#define XPAR_MUTEX_0_HIGHADDR 0x8260FFFF
#define XPAR_MUTEX_0_NUM_MUTEX 16
#define XPAR_MUTEX_0_ENABLE_USER 0

3. xparameters.h for microblaze_2


/* Definitions for peripheral XPS_MUTEX_0 */
#define XPAR_XMUTEX_NUM_INSTANCES 0


4. xparameters.h for microblaze_3


/* Definitions for peripheral XPS_MUTEX_0 */
#define XPAR_XMUTEX_NUM_INSTANCES 0

 

Could you help me to solve this problem?

Xilinx Employee
joshual
Posts: 188
Registered: ‎08-01-2007
0

Re: Xilinx mutex core dosn't support four PLB interface

how much MUTEX instaces in your design? and have you connect MUTEX BUS correctly? And also assign the address range?
Visitor
engmoneer
Posts: 7
Registered: ‎04-27-2010
0

Re: Xilinx mutex core dosn't support four PLB interface

Only one mutex instance. The mutex bus also connect correctly SPLB0 to PLB_0, SPLB1 to PLB_1, SPLB2 to PLB_2 and SPLB3 to PLB_3. The address of the mutex instance for the four microblaze is like this:

 

 

C_SPLB0_BASEADDR: 0x82400000

C_SPLB0_HIGHADDR: 0x8240FFFF

 

C_SPLB1_BASEADDR: 0x82600000

C_SPLB1_HIGHADDR: 0x8260FFFF

 

C_SPLB2_BASEADDR: 0x82800000

C_SPLB2_HIGHADDR: 0x8280FFFF

 

C_SPLB3_BASEADDR: 0x82A00000

C_SPLB3_HIGHADDR: 0x82A0FFFF

C_SPLB3_BASEADDR