Hi,
I've defined a custom SOC on V5FXT using an external DDR2 1Gbits chip.
It is connected to the PPC440 on its MC port with the PPC440mc_ddr2_v2_00_a peripheral.
I use ISE and EDK 10.1.3 and modelsim designer PLUS 6.3f, compilation is fine but when I launch simulation I get the following :
# ** Error: (vsim-3389) C:/Xilinx101/EDK/hw/XilinxProcessorIPLib/pcores/ppc440mc_ddr2_v2_00_a/hdl/verilog/ddr2_top.v(191): Port 'RDY' not found in the connected module (1st connection).
# Region: /fpga_acqgen3_bench/fpga/core_inst/v2p_inst/socinst/opbsdram/OpbSdram/u_ddr2_top/clk_reset
# ** Error: (vsim-3389) C:/Xilinx101/EDK/hw/XilinxProcessorIPLib/pcores/ppc440mc_ddr2_v2_00_a/hdl/verilog/ddr2_top.v(191): Port 'REFCLK' not found in the connected module (2nd connection).
# Region: /fpga_acqgen3_bench/fpga/core_inst/v2p_inst/socinst/opbsdram/OpbSdram/u_ddr2_top/clk_reset
# ** Error: (vsim-3389) C:/Xilinx101/EDK/hw/XilinxProcessorIPLib/pcores/ppc440mc_ddr2_v2_00_a/hdl/verilog/ddr2_top.v(191): Port 'RST' not found in the connected module (3rd connection).
# Region: /fpga_acqgen3_bench/fpga/core_inst/v2p_inst/socinst/opbsdram/OpbSdram/u_ddr2_top/clk_reset
# ** Fatal: (vsim-3365) C:/Xilinx101/EDK/hw/XilinxProcessorIPLib/pcores/ppc440mc_ddr2_v2_00_a/hdl/verilog/ddr2_top.v(191): Too many port connections. Expected 14, found 17.
# Time: 0 ps Iteration: 0 Instance: /fpga_acqgen3_bench/fpga/core_inst/v2p_inst/socinst/opbsdram/OpbSdram/u_ddr2_top/clk_reset File: C:/Xilinx101/EDK/hw/XilinxProcessorIPLib/pcores/ppc440mc_ddr2_v2_00_a/hdl/verilog/clk_reset.v
# FATAL ERROR while loading design
On my PC I only have one version of ISE/EDK and one version of modelsim, librairies are compiled with compxlib and compdeklib utilities.
But it looks like modelsim uses others files becaus when I open the files of the DDR2 preripheral in the EDK librairy they seem correct !
Does someone had the same problem ???
