General Technical Discussion

[mingyuexin1]

In my design, I have two custom IP, which use AXI stream, but the source is 32 bit width, the destination is 8 bit width, I'm wondering whether there is any IP in xilinx that can convert from 32 bit to 8 bit?

Do I have to write an conversion interface by myself?

[mingyuexin1]

Any reply will be appreciated. Thanks in advance!

[bwiec]

The AXI Interconnect is capable of upsizing and downsizing like this.

[mingyuexin1]

Thank you very much for the information.

But my IP have AXI stream interface, but the AXI interconnect core is for AXI/AXI lite.

The following sentence is in documentations of AXI interconnect core.

"The AXI Interconnect core is intended for
memory-mapped transfers only; AXI4-Stream transfers are
not applicable. IP with AXI4-Stream interfaces are generally
connected to one another, and to DMA IP."

[bwiec · Accepted solution]

Sorry for my being unclear. I meant the AXI Stream Interconnect:

http://www.xilinx.com/support/documentation/ipinterconnect_axi-stream-interconnect.htm

[mingyuexin1]

Thanks very much for the clarification!!!

[ptorruella]

Hello there,

I'm having some problems to simulate the AXI-Stream Interconnect core.

When I try to do so I always get the following:

ERROR:HDLCompiler:104 - "/net/user/r1/unix/torruella/axi_interconnect/ipcore_dir/axi_mux_sim.vhd" Line 145: Cannot find <axis_interconnect_16x16_top> in library <axis_interconnect_v1_0>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:854 - "/net/user/r1/unix/torruella/axi_interconnect/ipcore_dir/axi_mux_sim.vhd" Line 147: Unit <axi_mux> ignored due to previous errors.
ERROR:HDLCompiler:374 - "/net/user/r1/unix/torruella/axi_interconnect/ipcore_dir/axi_mux_sim.vhd" Line 190: Entity <axi_mux> is not yet compiled.
ERROR:HDLCompiler:69 - "/net/user/r1/unix/torruella/axi_interconnect/ipcore_dir/axi_mux_sim.vhd" Line 194: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "/net/user/r1/unix/torruella/axi_interconnect/ipcore_dir/axi_mux_sim.vhd" Line 195: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "/net/user/r1/unix/torruella/axi_interconnect/ipcore_dir/axi_mux_sim.vhd" Line 196: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "/net/user/r1/unix/torruella/axi_interconnect/ipcore_dir/axi_mux_sim.vhd" Line 197: <std_logic> is not declared.

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This even with a new project having only the core and a testbench. Do you know if I have to do something special besides the general procedure to use Ip-Cores generated with core gen?

I'm using v14.1 on linux. Thanks a lot for your time!