General Technical Discussion

[sraza]

Dear all,,

I need some assistance in this regard,

Has any one worked on 4dsp kit before...

Please do reply as I am severely facing trouble and I guess their respective forum and support is not that good since I have been posting there as well but no response untill now

Bests,

Shan

[ywu]

What trouble are you having?

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sraza wrote:

Dear all,,

I need some assistance in this regard,

Has any one worked on 4dsp kit before...

Please do reply as I am severely facing trouble and I guess their respective forum and support is not that good since I have been posting there as well but no response untill now

Bests,

Shan

---

[agaugue]

hi,

I work on a 4DSP FMC126 mezza board.

I have no responces for one week since I asked the CPLD code of the card to upgrade it with new features,

but they usualy responde within 2 days.

cheers,

Vincent

[sraza]

I do not have the modelsim xe or modelsim se...

can I run simulation on ISIM,Modelsim PE does not work with mixed language support, while my design is in Verilog, and the files generated by Steller IP is in VHDL

In the manual it is written as follows :

Modelsim is required in order to simulate projects created by StellarIP and compiled using Xilinx tools. Different simulators can be used to simulate the design, but the various Modelsim macros (compile.do) should be rewritten in consequence.

 so can you tell me how to do that or any solution which can get me to the simulation....

I have not used modelsim though with ISE any time, but separetely, with ISE I use ISIM

Please

[rcingham]

Maybe you could post an example 'compile.do' macro/script, and some ISIM boffin (therefore not me) might tell you how to change it.

[ywu]

I am afraind that modifying CPLD code is something you will have to work with 4DSP. Having said that, the FPGA can change some settings on the FMC card via SPI interface. What kind of new features are you adding?

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agaugue wrote:

hi,

I work on a 4DSP FMC126 mezza board.

I have no responces for one week since I asked the CPLD code of the card to upgrade it with new features,

but they usualy responde within 2 days.

cheers,

Vincent

---

[sraza]

Dear all,

Thank you for your reply. While I am working on simulation thing. I have one more question.

I am hopeful you would not mind answereing in the same discussion. I find little help from their forum and that too quite late.

This is the question again for 4DSP software Stellar IP.

I have my design in Verilog, now I have to integrate to the 4DSP development kit.
Can any one guide me how to make the star out of my verilog designs, I have 3 verilog modules, all of them interfaced to each other, what should be my approach. What are the steps to make the stars out of them...

btw, Is verilog supported by the IPsteller, since then it has to create the mixed signal design


Best Regards,
Shan

[sraza]

I am including the Image preocessing block that I have designed in Verilog.

Now seriously I am not getting idea, how to communicate all the stuff together, the wormholes, STARs, although I have the initial idea of doing all this using c++ code calling functions to invoke the STARs, but I cannot grasp the initial point and then the complete way through it to the final stage, I have posted the image that might help you what I am trying to do. I think I have included the important details, (minor details are not here).

Eagerly waiting for a reply