General Technical Discussion

[jmca]

Hi all,

I'm trying to write a VHDL package to define constants to be used in register address decoding in my design. The design has a DSP interface component which acts as slave of an EMIF bus and as master of an internal register bus.

There are 7 top level slaves for this register bus, and each one of those hasa given number of sub-slaves.

My goal for the address decoding is to have a single function to be called in a sequential process at each top level slave , being able to take a 2-D array of user defined record type (the registers). I'm trying the following definitions:

"

type t_dsp_register is
record
  slv_sel : std_logic_vector(2 downto 0);  -- slave select mux ctrl: up to 7 sub-blocks  per regbus slave.
  name  : t_register_name;
  addr    : std_logic_vector(c_num_addr_bits-1 downto 0);
  data    : std_logic_vector(c_reg_dim - 1 downto 0);
  en       : std_logic; -- used for > 16 bit registers
end record;

-- t_reg_slave: rows = sub-slave index, columns = register index within sub-slave
type t_reg_slave is array (natural range <>,natural range <>) of t_dsp_register;
type t_reg_subslave is array (natural range <>) of t_dsp_register;

constant c_slv_max : integer range 1 to 7 := 7;
constant c_regs_max: integer range 1 to 63 := 63;

constant c_ana_ctrl_slaves : integer range 1 to c_slv_max := 4;
constant c_ana_ctrl_num_regs : integer range 1 to c_regs_max := 33;
constant c_tsg_num_regs : integer range 1 to c_regs_max := 21;
constant c_atgc_num_regs : integer range 1 to c_regs_max := 2;
constant c_afe_num_regs : integer range 1 to c_regs_max := 4;
constant c_trx_num_regs : integer range 1 to c_regs_max := 6;

constant c_tsg_regs : t_reg_subslave(1 to c_tsg_num_regs) := (
(c_TSG.id ,TSIG_REG_1, X"c0200300" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_2, X"c0200312" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_3, X"c0200316" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_4, X"c020031a" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_5, X"c020031c" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_6, X"c020031e" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_7, X"c0200320" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_8, X"c0200322" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_9, X"c0200324" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_10, X"c0200326" , X"0000" ,'0'),
(c_TSG.id ,TSIG_REG_11, X"c0200328" , X"0000" ,'0'),
(c_TSG.id ,TSIG_REG_12, X"c020032a" , X"0000" ,'0'),
(c_TSG.id ,TSIG_REG_13, X"c020032c" , X"0000" ,'0'),
(c_TSG.id ,TSIG_REG_14, X"c020032e" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_15, X"c0200330" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_16, X"c0200332" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_17, X"c0200334" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_18, X"c0200336" , X"0000" ,'1'),
(c_TSG.id ,TSIG_REG_19, X"c0200338" , X"0000" ,'0'),
(c_TSG.id ,TSIG_REG_20, X"c020033a" , X"0000" ,'0'),
(c_TSG.id ,TSIG_REG_21, X"c020033c" , X"0000" ,'0')
  );

constant c_atgc_regs : t_reg_subslave(1 to c_atgc_num_regs) := (
(c_ATGC.id ,TEE_PROBE_RESET_REG, X"c0200800" , X"0000" ,'0'),
(c_ATGC.id ,TEE_PROBE_MODE, X"c0200802" , X"0000" ,'0')
  );

constant c_afe_regs : t_reg_subslave(1 to c_afe_num_regs) := (
(c_AFE.id ,TEE_PROBE_MODE, X"c0200802" , X"0000" ,'0'),
(c_AFE.id ,TEE_TEST1_REG, X"c0200804" , X"0000" ,'0'),
(c_AFE.id ,TEE_TEST2_REG, X"c0200806" , X"0000" ,'0'),
(c_AFE.id ,TEE_TEST3_REG, X"c0200808" , X"0000" ,'0')
  );

constant c_trx_regs : t_reg_subslave(1 to c_trx_num_regs) := (
(c_TRX.id ,TEE_INIT_PROBE_POS_REG, X"c020080c" , X"0000" ,'0'),
(c_TRX.id ,TEE_HYSTERESIS_REG, X"c020080e" , X"0000" ,'0'),
(c_TRX.id ,TEE_ORTO_REG, X"c0200810" , X"0000" ,'0'),
(c_TRX.id ,TEE_CENTER_POS_REG, X"c0200812" , X"0000" ,'0'),
(c_TRX.id ,TEE_START_POS_REG, X"c0200814" , X"0000" ,'0'),
(c_TRX.id ,TEE_END_POS_REG, X"c0200816" , X"0000" ,'0')
  );

constant c_ana_ctrl_regs : t_reg_slave(1 to c_ana_ctrl_slaves , 1 to c_ana_ctrl_num_regs) :=
   (c_tsg_regs, c_atgc_regs, c_afe_regs, c_trx_regs);

"

The Check Syntax process for the package crashes with the following error:

Compiling vhdl file "C:/ssci2/502054123_view/hardware/csound/pd/ssci2/common/design/top/ssci2_if_pkg.vhd" in Library work.
ERROR:HDLParsers:3285 - "C:/ssci2/502054123_view/hardware/csound/pd/ssci2/common/design/top/ssci2_if_pkg.vhd" Line 1093. No array or record type can be found that has elements of types matching the aggregate.

Line 1093 is the declaration of c_ana_ctrl_regs constant. I don't see the error in concatenating those 1-D arrays to form up a 2-D arrays. All of them are declared as constrained...

Do you see the error?

Jose

[gszakacs]

I'm going to preface this by saying I'm not a VHDL expert so this is just a guess...

Is it possible that the major index of your two-dimentional array is the second one in the

declaration, rather than the first?  Then the declaration should look like:

constant c_ana_ctrl_regs : t_reg_slave(1 to c_ana_ctrl_num_regs , 1 to c_ana_ctrl_slaves) :=
   (c_tsg_regs, c_atgc_regs, c_afe_regs, c_trx_regs);

The other possibility is that XST doesn't like to break out the t_reg_subslave type into its

component elements when you use it to initialize the two-dimensional array.

-- Gabor

[rcingham]

Most synthesizers have problems with unconstrained 2-D VHDL arrays.

The following change may help:

type t_reg_subslave is array (natural range <>) of t_dsp_register;
type t_reg_slave is array (natural range <>) of t_reg_subslave;