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Newbie

Posts: 3

Registered: ‎03-26-2012

Interfacing DDR3 SDRAM memory controller to an Virtex 6 FPGA

‎04-20-2012 11:00 PM

HI,

can any 1 say me, IS MIG core generator usage for this problem is correct?
By using MIG can we generate a code for interfacing Controller to an FPGA?

THANK YOU IN ADVANCE.

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Visitor

Posts: 7

Registered: ‎04-05-2012

Re: Interfacing DDR3 SDRAM memory controller to an Virtex 6 FPGA

‎04-21-2012 06:50 PM

Yes. Please read ug406

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