Is there any way to integrate an ISE core into XPS?

mingyuexin1 · ‎04-22-2009

As I know (ISE 10.1), when using a core (generated by CORE generator) in ISE Project Navigator, one can instantiate the core in VHDL source code, the corresponding .ngc file must also be included into the project.

I have an custom IP core which is implemented in Qsys (Quartus), I would like to port it to XPS, the custom IP core includes an Altera fifo and a RAM, I want to use Xilinx fifo and RAM to replace it, but I have no idea how these two cores are integrated into custom IP for XPS. I'm thinking to instantiate these cores in my custom IP source file, but I do not know if I need to include fifo.xco, fifo.ngc file to the .PAO file? Are there any other files supposed to be included into .PAO file as well?

This is supposed to be implemented in ISE suite 14.1.

Does anybody have any suggestion?

I will appreciate any reply.

bwiec · ‎08-02-2011

I think the file you are looking for is a .bbd (.pao is only for HDL for synthesis).

Have a look at this manual:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/psf_rm.pdf

Specifically Chapter 6 on the Black Box Definition file

www.xilinx.com

bwiec · ‎08-02-2011

Also note that you can look at the structure of existing Xilinx pcores that are delivered as part of XPS. This will be a good example of how to set it up.

For example, this pcore uses a .bbd to specify synthesized .ngc netlists from cores:

C:\Xilinx\14.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v4_01_a

www.xilinx.com

sushantm · ‎04-02-2011

As I know (ISE 10.1), when using a core (generated by CORE generator) in ISE Project Navigator, one can instantiate the core in VHDL source code, the corresponding .ngc file must also be included into the project.

I have an custom IP core which is implemented in Qsys (Quartus), I would like to port it to XPS, the custom IP core includes an Altera fifo and a RAM, I want to use Xilinx fifo and RAM to replace it, but I have no idea how these two cores are integrated into custom IP for XPS. I'm thinking to instantiate these cores in my custom IP source file, but I do not know if I need to include fifo.xco, fifo.ngc file to the .PAO file? Are there any other files supposed to be included into .PAO file as well?

First thing first Qsys (Quartus) IP's are not supported/will not work under Xilinx environment as each of them is having its own predefined formats (filename extension) so Be Aware!

If you have a custom logic in verilog/vhdl you can use ISE to make your own digital circuit inside Xilinx device.

By creating a new project in ISE according to your requirement you pick readily available builtin FIFO's for particular device and many more Xilinx coregen tool.

After you have created the project and able to make the ngc file/able to test as well.

You can import this to edk using IMPORT Custom IP/Peripheral wizard.

What is IMPORT Custom IP/Peripheral wizard ? I am new to EDK where do I start ?

Video tutorials here link#1,link#2,link#3,

Alternatively refer this document.

Do you ever search on google ?If yes,

You should Follow existing thread!

--Sushant Mahajan
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