04-18-2012 08:43 PM
I want to check FPGA functionality & I/O pins functionality using "Selftest application" on my board. Which methods i can use to check these in my Selftest application?Please give some ideas.
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04-18-2012 11:16 PM
for checking the internal function (of your design) you could build some BIST module.
Read the integrated circuits section of
to get an idea.
Checking the I/Os is another thing. There you are leaving the FPGA and need stimuli and response controll outside the device. During board production this is normally done using In-Circuit testers and using the JTAG interface of ICs for checking the connections and I/O drivers.
If you design your board yourself you could use something like a second FPGA in parallel so both devices can check each other. But this method would be kind of complicated and costly too.
Another method would be to stimulate the already attached hardware outside the board and look for expected return signals. (e.g. doing some dummy read/writes on some external memory. If the readback is correct, the I/O drivers work.)
This method is cheaper, but very board specific and the tests are sometimes limited depending on the kind of attached hardware. (e.g. how to verify that the Txd output works? There's no standard return path. Or you spend a second I/O pin as input to sense Txd. But what if the sense input fails, while Txd works fine? Much effort for nothing or just an increase of failure points?)
So, what's your goal in detail?
Have a nice synthesis
04-19-2012 07:39 AM
A common approach to signals that go off board is to build a loop-back cable for testing.
Then you can drive signals out and check that they properly loop back to the cabled
04-20-2012 10:26 PM
Thanks for replies.I am planning to Selftest the board without connecting any loopback cable externally. As you suggested i can move in this path.
- FPGA IO pins 1 to 50 are connected to FPGA IO pins 51 to 100 externally(with loopback connector) using a connector
- Load FPGA File
- Toggle pin 1 and check pin 51 status
- Toggle pin 2 and check pin 52 status
- Same is done for all 50 pins
- Results are displayed in GUI which is displaying on PC.
But i think it's difficult to use loopback cable in larger families of FPGA (I/O pins will be more so connector size is also very small). because i should see connector compatibility. if i start doing compatibility to the connectors to connect loopback cable, number of connectors in the board will become more. So again board size will become increase.
Is there any better way to check the I/O functionality / short between I/O's / dameges of I/O pin?
04-22-2012 10:38 PM
what is the scenario behind this approach?
Is it for quality inspection after production of the board, or is it for board health monitoring after deployment at the point of work/custumer?
I doubt that your approach is benefitial to any of the above.
- Board manufacturers should have professional in circuit testers to ensure production quality. No need to invent this wheel again.
- Increasing the complexity of a board and/or using a larger device with twice the I/Os creates more possible points of failure, and how do you monitor it if the failure happens in your interface pins to the PC? Also, if the test runs just once (e.g. after power up) and then the board works for hours or longer, failures could appear just then (e.g. due to thermal changes) so what's the test good for?
Think about when you want to catch what kind of errors.
And also what's happening after or in between of tests.
This also helps you to determine what kind of extra tools (loopback cables etc.) might be required for your tests.
Also it makes some difference wether your tests have to be implemented besides the functional design or if you have to load a different bitfile for it.
Have a nice synthesis
04-27-2012 09:45 PM
Thank you for all your replies. I am going to use Loopback cable to test the I/O pins of FPGA. But one doubt i have is "2 or 3 I/O pins gone wrong because of some reason. Can i display this message while Selftest application is running 'This I/O's is not working' instead of displaying 'FPGA part is not working'. Is this very much difficult?
04-30-2012 12:59 AM
If you are able to display anything somehow after testing it should not bee too complicated to select the result string according to some conditions. You could even do sthg. like this:
Core Function: OK - IO Test: Fail
Core Function: Fail - IO Test: OK
So you have both infos in one string and only replace OK and Fail according to the test results
Have a nice synthesis