General Technical Discussion

[mboden89]

Firstly i'll explain the application of the FPGA and feel free to assist in any way you can. I am using an FPGA implemented onto the BASYS 2 board from digilent inc, to design an EMC & Crosstalk Interference Demonstrator to apply a signal to the i/p & o/p ports on the board and then around induction loops etc. Now i have successfully applied clock division to reduce the clock to 20MHz from 100MHz ready for use on the victim boards i have designed.

However the problem exists where i am trying to increase the voltage on the outputs using the pull up resistor to match it to the Vcco (LVCMOS33) should give me a 3.3 volts squarewave output. However after writing the code there are erros appearing as it states the following.

PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp JA1 is set but the tri state is not configured.

How do i correct this so that i can achieve the desired voltage output??

Regards

M Boden

[mcgett]

It a appears that you attempted to enable the weak internal PULLUP attribute on a normal output buffer. This will have no significant impact which is why the WARNING is issued.

[gszakacs]

LVCMOSS33 will drive very close to the Vcco supply rail under light loads, and as mentioned

adding the internal weak pullup will have little effect.  If you need more drive you probably

want to start by setting the drive strength to the maximum allowed for that pin (for Spartan 6

there are different maximum strengths on different banks - check the data sheet).  Using

the fastest slew rate will also create some overshoot on the signal, and in your case that

may be useful (most people try to avoid overshoot, but as I understand you want to generate

a strong noise-source).

-- Gabor

[mboden89]

Thanks for your replies people, The voltage on the ouput pins is very small compared to what i am expecting but I have found a way around that. The problem exists now that when monitoring the affect of varying the drive strength and slew rate this shows very little difference in the corresponding waveforms. This is vital that I see a difference with these changes, can i assume that the effect of the 'pullup' resistor will not make any difference for this.

To sum up my intentions I am using a Spartan 3E on the Basys 2 board to initially match the effects of a programmable oscillator (CMOS technology) when applying a 20 MHz squarewave around an induction loop. The signal being applied should be as near to a squarewave as is possible. 

Once I have accomplished this then my intentions are to apply this signal to a number of different demonstration boards for use in lectures by my project supervisor after I have left university. I would prefer the voltage on the output pins to be higher. 

I understand the description is vague but any help would be greatly appreciated.

Mark 

[gszakacs]

1)  Make sure that the voltage you observe on the pins is higher (near Vcco) when you remove the load.  If

this is not the case, you may have a problem with the power to the FPGA, or a problem with your measuring

equipment.  Remember that telling the tools that you want 3.3V CMOS on an output will not generate

a 3.3V signal unless the Vcco supply is actually at 3.3V.

2)  If you need more drive strength, you can parallel 2 or more output pins together.  Just make sure that

the code drives the same signal to all of these pins, and that they all have their output flip-flops located

in the IOB.  This minimizes the skew between the outputs and therefore minimizes any "fighting" between

the output drivers.

-- Gabor

[mcgett]

>  I would prefer the voltage on the output pins to be higher. 
What is the DC resistance of the induction loop?

[mboden89]

Right guys that problem is sorted, next problem that i can pick your brains with. I am seeing no variation what so ever in the varying egde rates. I have tried this with a capacitive load and resistive load and i see no difference what so ever. I would expect from a fast edge rate to gain some overshoot and opposite for the slow edge rate i.e. undershoot but I am seeing nothing what so ever.. any ideas guys?

Mark

[sauravs]

From the constraints guide,(pg 229), it can be seen that it is only valid to place a PULLUP on inputs, tristate outputs or bi-directional pad nets. This message can occur when the design conflicts this.

E.g. Placing a PULLUP on the output of a BUFR causes this error as the output of the BUFR is not any of the above options.