Hi,
I have attached the code which is topfile's of SPI whatever i generated through IP core.How to add UCF file(which ports i have to take)to the design to generate bitfile.If we connect SPI to FPGA clk,MOSI,MISO, will come into picture.Here so many ports are there.How to Prepare ucf file for this SPI code.
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entity topfile is
port
(
RST : in std_logic;
TFCLK : in std_logic;
TENB : out std_logic;
TDAT : out std_logic_vector(7 downto 0);
TPRTY : out std_logic;
TSOP : out std_logic;
TEOP : out std_logic;
TERR : out std_logic;
TSX : out std_logic;
TADR : out std_logic_vector(7 downto 0);
PTPA : in std_logic;
TX_DST_RDY : out std_logic;
TX_SRC_RDY : in std_logic;
TX_SOF : in std_logic;
TX_EOF : in std_logic;
TX_ADDR : in std_logic_vector(7 downto 0);
TX_DATA : in std_logic_vector(7 downto 0);
TX_ERR : in std_logic;
TX_HALT_TDAT : in std_logic;
TX_CAL_CLK : in std_logic;
TX_CAL_EN : in std_logic;
TX_CAL_WR_EN : in std_logic;
TX_CAL_ADDR : in std_logic_vector(8 downto 0);
TX_CAL_DATA : in std_logic_vector(7 downto 0);
TX_CAL_DATA_OUT : out std_logic_vector(7 downto 0);
TX_TADR : out std_logic_vector(7 downto 0);
TX_PTPA : out std_logic;
RFCLK : in std_logic;
RENB : out std_logic;
RDAT : in std_logic_vector(7 downto 0);
RPRTY : in std_logic;
RVAL : in std_logic;
RSOP : in std_logic;
REOP : in std_logic;
RERR : in std_logic;
RSX : in std_logic;
RX_SRC_RDY : out std_logic;
RX_DST_RDY : in std_logic;
RX_SOB : out std_logic;
RX_SOF : out std_logic;
RX_EOF : out std_logic;
RX_ADDR : out std_logic_vector(7 downto 0);
RX_DATA : out std_logic_vector(7 downto 0);
RX_ERR : out std_logic;
RX_ERRBUS : out std_logic_vector(7 downto 0)
);
end topfile;
Architecture behavioral of topfile is
signal tfclk_int : std_logic;
signal rfclk_int : std_logic;
signal tfclk_clk0 : std_logic;
signal rfclk_clk0 : std_logic;
signal tfclk_ibufg : std_logic;
signal rfclk_ibufg : std_logic;
signal tx_cal_clk_int : std_logic;
signal zero : std_logic := '0';
component spi3_link_v7_1_spi3_link_rx is
port (
RST : in std_logic;
RFCLK : in std_logic;
RENB : out std_logic;
RDAT : in std_logic_vector(7 downto 0);
RPRTY : in std_logic;
RVAL : in std_logic;
RSOP : in std_logic;
REOP : in std_logic;
RERR : in std_logic;
RSX : in std_logic;
RX_SRC_RDY : out std_logic;
RX_DST_RDY : in std_logic;
RX_SOB : out std_logic;
RX_SOF : out std_logic;
RX_EOF : out std_logic;
RX_ADDR : out std_logic_vector(7 downto 0);
RX_DATA : out std_logic_vector(7 downto 0);
RX_ERR : out std_logic;
RX_ERRBUS : out std_logic_vector(7 downto 0)
);
end component;
component spi3_link_v7_1_spi3_link_tx is
port (
RST : in std_logic;
TFCLK : in std_logic;
TENB : out std_logic;
TDAT : out std_logic_vector(7 downto 0);
TPRTY : out std_logic;
TSOP : out std_logic;
TEOP : out std_logic;
TERR : out std_logic;
TSX : out std_logic;
TADR : out std_logic_vector(7 downto 0);
PTPA : in std_logic;
TX_DST_RDY : out std_logic;
TX_SRC_RDY : in std_logic;
TX_SOF : in std_logic;
TX_EOF : in std_logic;
TX_ADDR : in std_logic_vector(7 downto 0);
TX_DATA : in std_logic_vector(7 downto 0);
TX_ERR : in std_logic;
TX_HALT_TDAT : in std_logic;
TX_CAL_CLK : in std_logic;
TX_CAL_EN : in std_logic;
TX_CAL_WR_EN : in std_logic;
TX_CAL_ADDR : in std_logic_vector(8 downto 0);
TX_CAL_DATA : in std_logic_vector(7 downto 0);
TX_CAL_DATA_OUT : out std_logic_vector(7 downto 0);
TX_PTPA : out std_logic;
TX_TADR : out std_logic_vector(7 downto 0)
);
end component;
begin
spi3_link_rx0 : spi3_link_v7_1_spi3_link_rx
port map (
RST => RST,
RFCLK => rfclk_int,
RENB => RENB,
RDAT => RDAT,
RPRTY => RPRTY,
RVAL => RVAL,
RSOP => RSOP,
REOP => REOP,
RERR => RERR,
RSX => RSX,
RX_SRC_RDY => RX_SRC_RDY,
RX_DST_RDY => RX_DST_RDY,
RX_SOB => RX_SOB,
RX_SOF => RX_SOF,
RX_EOF => RX_EOF,
RX_ADDR => RX_ADDR,
RX_DATA => RX_DATA,
RX_ERR => RX_ERR,
RX_ERRBUS => RX_ERRBUS
);
spi3_link_tx0 : spi3_link_v7_1_spi3_link_tx
port map (
RST => RST,
TFCLK => tfclk_int,
TENB => TENB,
TDAT => TDAT,
TPRTY => TPRTY,
TSOP => TSOP,
TEOP => TEOP,
TERR => TERR,
TSX => TSX,
TADR => TADR,
PTPA => PTPA,
TX_DST_RDY => TX_DST_RDY,
TX_SRC_RDY => TX_SRC_RDY,
TX_SOF => TX_SOF,
TX_EOF => TX_EOF,
TX_ADDR => TX_ADDR,
TX_DATA => TX_DATA,
TX_ERR => TX_ERR,
TX_HALT_TDAT => TX_HALT_TDAT,
TX_CAL_CLK => tx_cal_clk_int,
TX_CAL_EN => TX_CAL_EN,
TX_CAL_WR_EN => TX_CAL_WR_EN,
TX_CAL_ADDR => TX_CAL_ADDR,
TX_CAL_DATA => TX_CAL_DATA,
TX_CAL_DATA_OUT => TX_CAL_DATA_OUT,
TX_PTPA => TX_PTPA,
TX_TADR => TX_TADR
);
tfibufg :IBUFG
port map (
O => tfclk_ibufg,
I => TFCLK
);
rfibufg :IBUFG
port map (
O => rfclk_ibufg,
I => RFCLK
);
tfdcm: DCM
port map (
CLK0 => tfclk_clk0,
CLK180 => OPEN,
CLK270 => OPEN,
CLK2X => OPEN,
CLK2X180 => OPEN,
CLK90 => OPEN,
CLKDV => OPEN,
CLKFX => OPEN,
CLKFX180 => OPEN,
LOCKED => OPEN,
PSDONE => OPEN,
STATUS => OPEN,
CLKFB => tfclk_int,
CLKIN => tfclk_ibufg,
DSSEN => zero,
PSCLK => zero,
PSEN => zero,
PSINCDEC => zero,
RST => RST
);
rfdcm: DCM
port map (
CLK0 => rfclk_clk0,
CLK180 => OPEN,
CLK270 => OPEN,
CLK2X => OPEN,
CLK2X180 => OPEN,
CLK90 => OPEN,
CLKDV => OPEN,
CLKFX => OPEN,
CLKFX180 => OPEN,
LOCKED => OPEN,
PSDONE => OPEN,
STATUS => OPEN,
CLKFB => rfclk_int,
CLKIN => rfclk_ibufg,
DSSEN => zero,
PSCLK => zero,
PSEN => zero,
PSINCDEC => zero,
RST => RST
);
tfbufg : BUFG
port map (
O => tfclk_int,
I => tfclk_clk0
);
rfbufg : BUFG
port map (
O => rfclk_int,
I => rfclk_clk0
);
calbufg: BUFG
port map (
O => tx_cal_clk_int,
I => TX_CAL_CLK
);
end behavioral;
Thanks You in Advance,
Mahesh Hegde.
