General Technical Discussion

[venkatesh.g]

I am trying to shift data from register to register at the transition of a clock.This is the code I have used

always @(posedge clk or negedge clk)

begin

sr_cnt1<=data_in;
sr_cnt2<=sr_cnt1;
sr_cnt3<=sr_cnt2;

end

data_in,sr_cnt3,sr_cnt2,sr_cnt1 are 10 bit registers

It works fine for a majority of the iterations but for some iterations the data_in value is directly stored in sr_cnt3 as well as sr_cnt2 at the same time while running the behavioral simulation. Any idea why this happens? How to prevent it ?

[rcingham]

What technology is this aimed at?
What simulator are you using?

[venkatesh.g]

Spartan6 xc6slx100t-3fgg900

Xilinx ISE Simulator 13

[eilert]

Hi,

synthesis tools for FPGAs do not infer dual-edge clocked FFs.

The FPGA logic fabric does not have this kind of elements.

(There are some dual edge clocked FFs in the I/O cells though, but these are only available by instantiation for special purposes)

Have a nice synthesis

  Eilert

[venkatesh.g]

Hi,

The code works just fine with dual edge trigerred FFs on many other occassions. It is just this one instance where it is problematic. The clock which I have used comes from a PLL. Will this cause an issue? 

How else can we give a dual edge triggered FF (without doubling the clock)?

Or will the design work once placed on FPGA?

[rcingham]

To know why this isn't working in your simulation, you will have to post more code, including the testbench.

BUT, the Xilinx tools will NOT implement dual-edge FFs in an FPGA.

[gszakacs]

The code works just fine with dual edge trigerred FFs on many other occassions.

For synthesis or simulation?  If synthesis what part were you targetting?

As far as I know, only CoolRunner II supports this sort of dual-edge flip-flop inference.

For simulation, you can have issues with the first stage of your shift register if

the input signal has no hold time and the clock is buffered in a way that can cause

delay (e.g. going through a PLL).  However the following stages should work correctly

because you have them in the same always block on the same clock signal and

use non-blocking assignments.  If this is not the case, can you post a screen-shot

of your simulation waveform?

-- Gabor

[eilert]

Hi,

this is no issue of the clock source, but of the capability of the elements in an FPGAs logic fabric.

Simulation can fool you a lot, but syntheses takes you straight back to reality.

If you are using the IOBs DDR-FFs then you also have to deal with two data inputs or outputs, (regarding wether its an input or output DDR-FF). But even if you would instantiate them and wire them up correctly, their number is very limited and the result will probably have a slow timing since you are winding your signals only along the IOBs causing heavy delays.

So, creating a somewhat more tricky circuit can probably help you.

e.g.

You can have two parallel shift registers, one working on the rising edge, the other on the falling edge.

Thus you end up with two data streams, but the data would be sampled and shifted on both edges at the input.

Can you deal with two data streams in the following circuits?

However, you can use a ODDR2 to combine these two signals into one common output.

(Likewise, for sampling an input pin you can also use a IDDR2.)

However, take a look at the documentation of the IDDR2 and ODDR2 primitives, to understand how they work.

Then you can think about how to use these parts in your design and what other circuitry is needed for your shift register.

Have a nice synthesis

  Eilert