04-11-2012 01:47 AM
i would like to ask if its possible to access 2 adresses of the same ram at the same time, i mean does this make a problem in the synthesis of the ram or its better to make it in 2 different steps ?
if rising_edge(clk) then
04-11-2012 02:08 AM - edited 04-11-2012 02:14 AM
Your example requires three (not two) concurrent RAM accesses: a write access and two read accesses, with independent addresses for each..
From the ISE Language Templates>VHDL>Synthesis Constructs>Coding Examples>RAM>BlockRAM>Dual Port:
-- Ensure that the <ram_name> is correctly defined. Please refer to the RAM Type
-- Declaration template for more info.
-- The following code must appear before the "begin" keyword in the architecture
constant ADDR_WIDTH : integer := <num_addr_bits>;
constant DATA_WIDTH : integer := <data_width>;
type <ram_type> is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal <ram_name>: <ram_type>;
-- If using Dual Port, 2 Clocks, 2 Read/Write Ports use the following definition for <ram_name>
shared variable <ram_name>: <ram_type>;
if (<clock>'event and <clock> = '1') then
if (<enableA> = '1') then
if (<write_enableA> = '1') then
<ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
<ram_outputB> <= <ram_name>(conv_integer(<addressB>));
Or you can simply use the CoreGen Block RAM wizard.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
04-11-2012 02:49 AM
in the case that i am using a FSM that takes the output of the memory at certian states whould this be ok
and does the outputs from the ram should not exceed 2 at the same time ?
04-11-2012 03:41 AM
If you instantiate (or let the tools infer) a Dual Port RAM, as Bob helpfully explicitly stated, you can read from two addresses at the same time.
If you do not instantiate (or let the tools infer) a Dual Port RAM, you will not be able to do this.
If you need to access different parts of the same data array that is not a DP RAM at the same time, you could consider leaving it as a set of registers and not use a RAM at all.
Using an FSM should make no difference to this at all.
"That which we must learn to do, we learn by doing." - Aristotle