General Technical Discussion

[ahmedmohamed_45]

HI

i would like to ask if its possible to access 2 adresses of the same ram at the same time, i mean does this make a problem in the synthesis of the ram or its better to make it in 2 different steps ?

process(clk)

begin

if rising_edge(clk) then

ram(addr)<=din;

end if;

end process;

dout1<=ram(3);

dout2<=ram(5); 

[eteam00]

Your example requires three (not two) concurrent RAM accesses: a write access and two read accesses, with independent addresses for each..

From the ISE Language Templates>VHDL>Synthesis Constructs>Coding Examples>RAM>BlockRAM>Dual Port:

-- Ensure that the <ram_name> is correctly defined. Please refer to the RAM Type
-- Declaration template for more info.

-- The following code must appear before the "begin" keyword in the architecture
-- body.
constant ADDR_WIDTH : integer := <num_addr_bits>;
constant DATA_WIDTH : integer := <data_width>;

type <ram_type> is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal <ram_name>: <ram_type>;

-- If using Dual Port, 2 Clocks, 2 Read/Write Ports use the following definition for <ram_name>
shared variable <ram_name>: <ram_type>;

process (<clock>)
begin
   if (<clock>'event and <clock> = '1') then
      if (<enableA> = '1') then
         if (<write_enableA> = '1') then
            <ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
         end if;
         <ram_outputA> <= <ram_name>(conv_integer(<addressA>));
         <ram_outputB> <= <ram_name>(conv_integer(<addressB>));
      end if;
   end if;
end process;

Or you can simply use the CoreGen Block RAM wizard.

-- Bob Elkind

[ahmedmohamed_45]

Dear sir,

in the case that i am using a FSM that takes the output of the memory at certian states whould this be ok

when s1=>

 dout1<=ram(3);

 dout2<=ram(5);

nxt_state<=s0;

and does the outputs from the ram should not exceed 2 at the same time ?

[hgleamon1]

If you instantiate (or let the tools infer) a Dual Port RAM, as Bob helpfully explicitly stated, you can read from two addresses at the same time.

If you do not instantiate (or let the tools infer) a Dual Port RAM, you will not be able to do this.

If you need to access different parts of the same data array that is not a DP RAM at the same time, you could consider leaving it as a set of registers and not use a RAM at all.

Using an FSM should make no difference to this at all.

Regards,

Howard