trounds wrote:
Thanks for the quick response. I only specify an initial condition with this is generated as part of simulation. There is no initial condition for the code specific to synthesis. Why doesn't the software know this?
Your code in the first post in this thread looks correct.
Are you sure you set the generic properly in the synthesis options? I assume that the SIM_ENB constant is set by a generic in the entity's port list, and I futher assume that the entity in question isn't the top level of the FPGA design.
You have to make sure that the generic filters all the way up to the top of the hierarchy, so it can be set in the synthesis and simulation options. Otherwise, the tools will assume the default (which isn't clear from the code you posted) and honestly, I don't know what happens in absence of a default.
My guess is that the synthesis tool is actually using the SIM_RESULT_RAM.
And for what it's worth: when you infer a memory, the simulation tool doesn't magically know that your code refers to a specific library element. It just simulates exactly what you code.
Finally, what Bob suggests about an initializer should be correct. So something like:
type lutram_t is array (0 to 15) of std_logic_vector(47 downto 0);
signal lutram : lutram_t := (others => (others => '0')); -- <<== this is the initializer
signal addr : natural range 0 to 15;
signal foo : std_logic_vector(47 downto 0);
u_lutram : process (clk) is
begin
if rising_edge(clk) then
if we = '1' then
lutram(addr) <= foo;
end if;
end if;
end process u_lutram;
that oughta do it.
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Yes, I do this for a living.
