General Technical Discussion

[hchandra]

We are using triple rate SDI IP core on Spartan-6. To support all standards, we need to provide 2 different reference clocks of frequencies 148.5MHz and 148.5/1.001MHz. Can 148.5/1.001 MHz be generated inside the Spartan-6 device in any way using 148.5MHz to be driven to GTP reference clock. This looked impossible with DCM which I already tried out.

Also can you please suggest an oscillator IC which will generate 148.5/1.001 MHz so that we can provide this clock externally?MAXIM  or TI or IDT the best suited in your opinion.

regards

chandra

[bwiec]

For high speed applications, it is recommended that your transceivers refclocks be driven from an oscillator.

Looking at DS849 page 8, it says:

"The Triple-Rate SDI transmitter supports all five supported SDI bit rates, requiring just two different GTP reference
clock frequencies to do so. Table 3 shows the supported GTP reference clock frequencies for each bit rate. If
148.5 MHz is used for one reference clock frequency, 148.5/1.001 MHz must be used for the other. Or, if 74.25 MHz
is used for one reference clock frequency, 74.25/1.001 MHz must be used for the other. The two reference clock
frequencies can be input to the FPGA as one reference clock, using an external switch or a clock generator that can produce either required reference clock frequency or as two separate reference clocks, one of each frequency, using the clock multiplexer built into the GTP transceiver to switch between the two reference clocks."

I also wanted to point out that on the RX side:

"The Triple-Rate SDI receiver uses a single GTP reference clock frequency to receive all five supported SDI bit rates.
The receiver automatically determines the incoming SDI bit rate and configures itself and the GTP transceiver
appropriately for that SDI mode."

In general, there is a lot of discussion on clocking in the documentation. See DS849, UG824, and XAPP1076

[ccon67]

Which clock generator/synthesizer do you want?

You need to ask yourself this queiton jitter vs. accuracy? which one you prefer, assume you have no problem to add one on your board

AS other pointed out, you need to generate two frequencies outside the FPGA then eihter mux them outside or let the FPGA to select one.

The FPGA DCM does not have that fine resolution to perform   x 1001  /1000

May I ask, is this core come free or we have to pay for it ?

[bwiec]

The core is free. Actually, source code is also provided with xapp1076

[tomctomc]

I will be implementing the SDI triple rate function using a Virtex 6 device and am looking at the xapp1075 and DS848 as a reference point. My focus is on the SDI receiver function.

1) Does the GTX function on its own without the SDI core support to properly recovery the triple rate clock. Once the recover clock is availble I will perform my own SDI sync search and decoding.

2) In addition, the xapp1075 document has an DRP interface between the GTX and the triple rate core. it is not clear what is the purpose of this port during the receiver function? Does the triple rate core need to configured the GTX first before the GTX recovery section function properly, if this is true then the GTX can't automatically recover the receiving clock.

Thanks,

[eteam00]

tomctomc,

Please do not cross-post.  Your thread in the Virtex forum is sufficient.  Let's keep the discussion in one place.

Thank you.

-- Bob Elkind