General Technical Discussion

[klawetter]

The Spartan 6 Configuration guide (UG380) doesn't state whether a non-continuous cclk can be used in the slave serial configuration mode. UG380 states that a non-continuous clock is allowed for SelectMap configuration but what about for the slave serial configuration mode?

[eteam00]

Non-continuous CCLK will work for Spartan-6 configuration in slave serial mode.  For example, there is a long and honoured tradition of support for external processors configuring FPGAs with the use of 'bit-banging' for both CCLK and configuration DATA.

If this was not the case, additional specifications for CCLK waveforms would be required, including minimum frequency and maximum jitter.  Such specifications are not present in DS162, Table 47 -- the requirements for Slave Serial mode programming are quite simple.

-- Bob Elkind

[klawetter]

Thanks, Bob. I suspected, due to the lack of a max cclk period spec, that it was possible to use a non-continuous clock, but I found it odd that non-continuous operation was explicitly mentioned for selectMAP mode but not serial mode. Have you actually configured a Spartan 6 in slave serial mode using a non-continuous clock?

[eteam00]

Have you actually configured a Spartan 6 in slave serial mode using a non-continuous clock?

No.  Please define the range of CCLK pulse widths (high or low) which you would consider 'non-continuous'.

But here are a few of the FPGAs I have configured in slave serial mode using 'bit-bang' (which some would consider an example of 'non-continuous' CCLK):

• 3000a series (I recall there was a maximum CCLK pulse width requirement)
• 4000a series
• Spartan
• Spartan-XL
• Spartan-II
• Spartan-IIIx
• Virtex-4
• Virtex-5

I have only used Spartan-6 in Master Serial (SPI) mode, so far.

Consider also that CCLK frequency is not static for Master Serial configuration mode.  A bit field in the configuration header can optionally direct the CCLK frequency to increase from default 'safe' setting.

-- Bob Elkind

[klawetter]

I will be configuring my device over a GigE LAN connection so the cclk will have indeterminate interruptions. I'm wondering if the Spartan 6 has some sort of timeout once configuration has begun and could a gap of sufficient length meet this timeout. I doubt that this is the case, but I would like explicit confirmation.

[eteam00]

Suggest you open a webcase.

-- Bob Elkind

[klawetter · Accepted solution]

Opened a webcase and here is the answer from Xilinx support:

"Yes you can use a non continuous CCLK for Slave serial mode.  This is fine.  Data will be clocked in on the rising edge of the clock."

Then I asked a follow-up question:

Question:  "So a CCLK discontinuity on the order of milliseconds would not cause the Spartan 6 to timeout during configuration?"

Xilinx Answer:  "That is correct."