General Technical Discussion

[weilings]

OK,here is all the **bleep** I got,and I referred to these three threads without any result,can you help me?

http://forums.xilinx.com/t5/Synthesis/XST-Warning-Message/td-p/62089

http://forums.xilinx.com/t5/Archived-ISE-issues/How-to-use-custom-versions-of-Library-symbols-in-ISE...

http://forums.xilinx.com/t5/Synthesis/Block-RAM-problem/m-p/183420

Reading design: mother_board.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "dpram_16.v" in library work
Module <dpram_16> compiled
No errors in compilation
Analysis of file <"mother_board.prj"> succeeded.
 
Compiling vhdl file "D:/ISE/learning/project/dpram/dpram/adda.vhd" in Library work.
Entity <address> compiled.
Entity <address> (Architecture <Behavioral>) compiled.
Compiling vhdl file "D:/ISE/learning/project/dpram/dpram/data_in_a.vhd" in Library work.
Entity <data_in_a> compiled.
Entity <data_in_a> (Architecture <Behavioral>) compiled.
Compiling vhdl file "D:/ISE/learning/project/dpram/dpram/data_in_b.vhd" in Library work.
Entity <data_in_b> compiled.
Entity <data_in_b> (Architecture <Behavioral>) compiled.
Compiling vhdl file "D:/ISE/learning/project/dpram/dpram/mother_board.vhd" in Library work.
Entity <mother_board> compiled.
Entity <mother_board> (Architecture <Behavioral>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <mother_board> in library <work> (architecture <Behavioral>).

Analyzing hierarchy for entity <address> in library <work> (architecture <Behavioral>).

Analyzing hierarchy for entity <data_in_a> in library <work> (architecture <Behavioral>).

Analyzing hierarchy for entity <data_in_b> in library <work> (architecture <Behavioral>).

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mother_board> in library <work> (Architecture <Behavioral>).
Entity <mother_board> analyzed. Unit <mother_board> generated.

Analyzing Entity <address> in library <work> (Architecture <Behavioral>).
Entity <address> analyzed. Unit <address> generated.

Analyzing Entity <data_in_a> in library <work> (Architecture <Behavioral>).
Entity <data_in_a> analyzed. Unit <data_in_a> generated.

Analyzing Entity <data_in_b> in library <work> (Architecture <Behavioral>).
Entity <data_in_b> analyzed. Unit <data_in_b> generated.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <address>.
    Related source file is "D:/ISE/learning/project/dpram/dpram/adda.vhd".
    Found 4-bit up counter for signal <temp>.
    Summary:
 inferred   1 Counter(s).
Unit <address> synthesized.

Synthesizing Unit <data_in_a>.
    Related source file is "D:/ISE/learning/project/dpram/dpram/data_in_a.vhd".
    Found 4-bit up counter for signal <temp>.
    Summary:
 inferred   1 Counter(s).
Unit <data_in_a> synthesized.

Synthesizing Unit <data_in_b>.
    Related source file is "D:/ISE/learning/project/dpram/dpram/data_in_b.vhd".
    Found 4-bit up counter for signal <temp>.
    Summary:
 inferred   1 Counter(s).
Unit <data_in_b> synthesized.

Synthesizing Unit <mother_board>.
    Related source file is "D:/ISE/learning/project/dpram/dpram/mother_board.vhd".
Unit <mother_board> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 3
 4-bit up counter                                      : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '5vsx50t.nph' in environment D:\ISE\ISE.
Reading core <dpram_16.ngc>.
WARNING:Xst:1474 - Core <dpram_16> was not loaded for <inst1> as one or more ports did not line up with component declaration.  Declared input port <WEA> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 3
 4-bit up counter                                      : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mother_board> ...

Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <douta<3>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<2>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<1>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<0>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<3>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<2>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<1>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<0>> driven by black box <dpram_16>. Possible simulation mismatch.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mother_board, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 12
 Flip-Flops                                            : 12

=========================================================================

=========================================================================
*                           Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_clk                            | BUFGP                  | 4     |
clk_data_inb                       | BUFGP                  | 4     |
clk_data_ina                       | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 1.397ns (Maximum Frequency: 715.820MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 0.823ns
   Maximum combinational path delay: 2.788ns

=========================================================================

Process "Synthesis" completed successfully

Started : "Launching ISE Text Editor to edit mother_board.vhd".
Recustomizing IP...
10.1 - Xilinx CORE Generator IP GUI Launcher K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
Finished Recustomizing.

[mcgett]

> OK,here is all the **bleep** I got,and I referred to these three threads without any result,can you help me?

You posted some material, but you didn't define the problem or the issue that you are trying to solve.  What is it?

[weilings]

WARNING:Xst:2036 - Inserting OBUF on port <douta<3>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<2>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<1>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<0>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<3>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<2>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<1>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<0>> driven by black box <dpram_16>. Possible simulation mismatch.

as is mentioned in the topic,the xst 2036 problem!

[mati80]

I have the same problem:

WARNING:Xst:2036 - Inserting OBUF on port <douta<3>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<2>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<1>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <douta<0>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<3>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<2>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<1>> driven by black box <dpram_16>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <doutb<0>> driven by black box <dpram_16>. Possible simulation mismatch.

Any solution??? 

Thanks!!!!

[pplaza]

 Hi,

I agree with Mcgett. We can't guess wht is your issue although we could try to do it. It will be more helpful if you provide more information, i.e. as wrote Mcgett, what is the problem? or the device you use or the ISE version or if you are using a IP core.

Pedro.

[pplaza]

Taking a quick look to your synthesis report, you can find the following warning above the famous warning number 2036:

WARNING:Xst:1474 - Core <dpram_16> was not loaded for <inst1> as one or more ports did not line up with component declaration.  Declared input port <WEA> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.

That's your main problem, I suppose.

You should take into account that XST parser are different for old and new FPGAs (i.e. Spartan-3 has a different parser than Spartan-6). This is important information.

The code you are trying to synthetize may be useful too.

[roycegains]

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