> Yeah, I know I suck at VHDL or any coding for that matter, I think that's patently obvious. I'm a hardware engineer, but for this project I happen to need to do some CPLD stuff.
Could you design it using gates and flip-flops in a schematic?
Also, if you get a 'trigger' during counting, is it ignored?
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"If it don't work in simulation, it won't work on the board."
