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Regular Contributor
ahmedmohamed_45
Posts: 80
Registered: ‎07-14-2010
0

VHDL works only with spartan 3AN

Hi,

 

I wrote a vhdl code that interface with a module through SPI communication protocol my code was done in FSM with next state logic, it worked perfectly with my spartan 3AN board but when i try it on ALTERA DE0-nano baord it didnt work at all although its pure VHDL what i understand is that vhdl is suitable for any FPGA, so can any body please explain to me whats happinig.another if i didnt use global  a reset for the code does it make difference ?

Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

SPI works only with spartan 3AN

You should tell the Altera support folks that SPI interfaces do not work on Altera devices.  This isn't true, but it should get their attention.

 

You should post this on some other user forum, though, and not here.  I don't think the Altera folks read these (Xilinx) user forums very often.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Expert Contributor
eilert
Posts: 2,084
Registered: ‎08-14-2007
0

Re: VHDL works only with spartan 3AN

Hi,

unfortunately you didn't post the error messages you were seeing.

Your question about the global reset makes me guess that you are having problems with that.

If you are using the STARTUP block and its GSR signal in your HDL code, then it isn't device independent anymore.

 

Check your sources for stuff that are Xilinx specific and replace it with the Altera equivalent, if possible.

Xilinx has a nice white paper about using resets in FPGAs. Parts of it can be applied to all FPGA designs, other parts are vendor specific. You have to sort it out by yourself.

 

Have a nice synthesis

  Eilert