05-08-2012 02:12 AM
Hello all, I'm new to working on FPGAs, I have a system generator model for my image processing. I have checked the model in simulations. I need to know how to calculate time consumed by the hardware. I'm executing my sysgen model on a Virtex2pro board.. Can anyone please help me out..
05-09-2012 05:33 AM
Set your "Simulink System Period" in the System Generator block to the value of your boards System Clock.
Look at your simulation and that's it.
Have a nice synthesis
05-12-2012 12:39 AM
Hello Sir, i tried changing the 'simulink system period' but many errors are popping out. I have used many blocks such as counter, SIngle port RAM and others, if i change the period, there are errors due to all these blocks. I was told to use 'Wavescope' or a 'Chipscope' block to find out the time consumption on hardware. But it says we cannot use a Chipscope in hardware co-simulation. I have attached the model with this comment. Please suggest me the necessary changes and help me in finding out the time consumed for my model in hardware..
The model is done in MATLAB R2007b. Thanks in advance..
05-13-2012 11:20 PM
of course you have to change the period in all sampling blocks according to the simulink Period.
That are for example all "Gateway In" blocks, Counters and registers etc.
The most convenient way is to define a variable "period" in the matlab workspace and change all period block properties to that name. Then it's also quite simple to do stuff like period*2 for blocks that should run at half speed (Downsampling systems and such).
Also you can make your simulationtime automatically adapt to the actual period value
Set the simulation end time to "(length(t) + pipelineoffset)*period". Of course pipelineoffset has to be defined in the workspace too.
(There are older threads that explain this in more detail, just search the forum.)
Don't let yourself scare by all these error messages. The way from a useless default design to a full configured model of something real needs a lot of property changing and some understanding on how simulink and sysgen work together.
Wavescope can be used to trace signals in teh simulation and with the markers you can measure the time between events if your period value is set to a meaningfu value that corresponds with the desired hardware settings. (A period of 1s is quite ridiculous for a hardware system in most cases) .
The same holds for chipscope, except that it works on the finished and configured device. The funny point is, that when you leave your period at one second, sysgen will create clock dividers to match the desired sample time. Wouldn't it be funny to have a finished design that runs slower than the simulation?
Of course chipscope makes no real sense in HW-cosim. The design is remotely controlled and therefore much slower than in reality. Tracing this behavior with chipscope is meaningless.
Have a nice simulation