Initially, you will probably want to choose a FPGA device family based on design specifications (type of high speed transceivers, number of I/Os, external memory requirements, operating frequency, cost). You can then synthesise your design for the largest device in that family. The report will tell you how many resources your design required (LUTs, FFs, BRAMs, DSPs, DCMs, etc.). Look at the FPGA family table to find the smallest part that satisfies your I/O requirement and contains the required number of these resources, plus a bit of margin. Synthesise for that part, and you're done (did you meet the cost requirement?)
I don't think there's an automated way to get the tools to tell you this, but don't forget that the design itself will influence the size of the FPGA required. You could do a thousand operations in parallel and require a very big part, but if latency isn't critical you could do the operations serially using only a single processing unit, perhaps at a higher speed. When you create an IP core like an FFT, there are options to control the use of BRAM and DSP blocks at the core generation stage. You would generally do this with an idea of the part you're planning to use in mind.
