04-18-2012 05:27 AM
Hi, what's the difference in using the input_jitter value together with the period constraint rather then just tightening the period?
input jitter: +/- 100 ps
period: 10 ns
Are constraints 1 and 2 equivalent?
1) TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50% INPUT_JITTER 100 ps;
2) TIMESPEC TS_clk = PERIOD "clk" 9.9 ns HIGH 50%;
Solved! Go to Solution.
04-18-2012 08:39 AM
None. If you know what you are doing.
One half the total peak to peak jitter is automatically subtracted from the minimum period by the tools, so you don't have to do this yourself.
You do have to enter the clock source jitter, and the system jitter (jitter created by your pcb layout, bypassing solution, IOs switching, etc.), while the clock jitter (MMCM, PLL, DCM) jitter is all calculated by the tools and added up.
If you don't know your system jitter, start with 100 ps peak to peak. In a very aggressive design, with poor bypassing, or lots of IOs strongly switching, it can be as much as 1000 ps, or even more. You can measure your system jitter by bringing the clock in question out on an IO pin useing the DDR IOB DFF, so that it may be measured externally.
Occasional data errors, or logic errors, are often caused by not taking jitter into account, and having insufficient slack in your timing.
Xilinx San Jose
04-25-2012 04:04 AM
Thanks for the answer, I have two follow up questions:
1) Do I understand you correct that the tools will forward my jitter constraint through the design (DCMs etc) (I am running ISE 11.4)? Can I confirm that the jitter is forwarded some way? Looking at my timing report for the Clock Uncertainty I see my input jitter (I have not added any other uncertanty to the clock constraint yet) but I don't see any jitter from the DCM added? Is this correct? I have attached my trace report file for reference.
2) I would like to meassure the system jitter as you sugest. Do you have any refernce to a "measure your system jitter for dummies" step by step guide? Do I need any other measuring equipment other then a oscilloscope?
04-25-2012 07:22 AM
1. Yes. The jitter is evaluated on every path, and requires that you enter a clock jitter, and a system jitter. 35ps P-P is what most crystals oscillators deliver, and 100ps to 1000ps is a reasonable system jitter number.
2. An oscilloscope is insufficient to measure peak to peak jitter, unless it has a jitter measurement analysis package as part of its function (high end scopes do today). If you have never done this, and do not know where to start, I suggest you go do (a lot) of reading on signal integrity, and jitter. Bypassing, decoupling, transmission lines, matching, and perhaps a refresher course for Maxwell's equations (not really required, but it is all about fields, and waves).
I suggested the method in my last post. You seem to missing a good P-P jitter measurement device. Perhaps you can go rent one. LeCroy, Agilent, and others make some very good ones. Setting up the equipment properly is somewhat of an art, so you may request the salesman for that equipment show you how its done. They also have some good applications notes.
Xilinx San Jose
04-25-2012 08:25 AM
No. Although that is useful if you are designing a GPS system.
Jitter is one of the most obscure issues with high speed digital design, and especially with serial links (multi-gigabit transceivers), so it is definitely something that is good to know. If you do become an expert in the field, you will be one of the very few.
A good place to start is reading Howard Johnson's books, like "High-Speed Digital Design, A Handbook of Black Magic."
Xilinx San Jose