A one of the module is attached here
module x_input_ctrl(clk, reset, si, request, fifo_ready, ri, fifo_write, dest);
input clk, reset, si, fifo_ready;
input [2:0] dest;
output ri;
output fifo_write;
output [7:0] request;
reg ri;
reg [7:0] request;
reg [1:0] cur_state;
reg [1:0] next_state;
reg toggle;
reg prepare;
reg [7:0] output_dest;
parameter X = 8'b10101001, YP = 8'b10100110, YN = 8'b10011010, PE = 8'b01101010, NO = 8'b10101010, PENDING = 8'b00000000;
parameter STATE0 = 2'b00, STATE1 = 2'b01, STATE2 = 2'b10, STATE3 = 2'b11;
assign fifo_write = ri & si;
always @(dest)
begin
if (dest == 3'b001 || dest == 3'b010)
output_dest = X;
else if (dest == 3'b011)
output_dest = YP;
else if (dest == 3'b100)
output_dest = YN;
else if (dest == 3'b101)
output_dest = PE;
else
output_dest = NO;
end // always @ (dest)
always @(posedge fifo_ready)
toggle = ~toggle;
//output FSM
//state memory block
always @(posedge clk)
if (reset) begin
cur_state <= STATE0;
toggle <= NO;
end
else
cur_state <= next_state;
always @(clk, next_state, reset)
if (reset)
prepare = 1;
else if (clk == 0 && next_state == STATE1)
prepare = 0;
else
prepare = 1;
//next state logic
always @(si, fifo_ready, reset, cur_state)
case (cur_state)
STATE0: if (si) next_state = STATE1;
else next_state = STATE0;
STATE1: if (!fifo_ready) next_state = STATE2;
else next_state = STATE1;
STATE2: if (si && fifo_ready) next_state = STATE1;
else if (si && !fifo_ready) next_state = STATE3;
else if (!si && fifo_ready) next_state = STATE0;
else next_state = STATE2;
STATE3: if (fifo_ready) next_state = STATE1;
else next_state = STATE3;
endcase // case(cur_state)
//output logic block
always @(cur_state, toggle, prepare)
case (cur_state)
STATE0:
if (prepare == 0) begin
ri = 1'b1; request = PENDING;
end
else begin
ri = 1'b1; request = NO;
end
STATE1: begin
ri = 1'b0; request = output_dest;
end
STATE2:
if (fifo_ready) begin
ri = 1'b1; request = PENDING;
end
else begin
ri = 1'b1;
end
STATE3:
if (fifo_ready) begin
ri = 1'b0; request = PENDING;
end
else begin
ri = 1'b0;
end
endcase // case(cur_state)
endmodule
