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Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-17-2012 05:43 AM
It really sounds like something is wrong with the electrical interface if you need to invert the
data signal. Have you tried Bob's suggestion of just routing Rx data to Tx Data to see if
the electrical interface is OK?
-- Gabor
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-17-2012 06:04 AM
Logic '0' = RS232 '+'
Logic '1' = RS232 '-'
------------------------------------------
"If it don't work in simulation, it won't work on the board."
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-17-2012 06:39 AM
- clock is not buffered but still works fine.
Try buffering the clock. Use a BUFG. Don't bother with anything else until you have tried this.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-17-2012 06:51 AM
eteam00 wrote:
- clock is not buffered but still works fine.
Try buffering the clock. Use a BUFG. Don't bother with anything else until you have tried this.
-- Bob Elkind
I synthesized his code using ISE 13.4 and it automatically adds a BUFG on the 9600 baud clock
as well as the input clock. This still appears to be an electrical issue.
-- Gabor
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
[ Edited ]
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05-17-2012 07:29 AM - edited 05-24-2012 04:36 AM
I synthesized his code using ISE 13.4 and it automatically adds a BUFG on the 9600 baud clock
as well as the input clock. This still appears to be an electrical issue.
Thanks, Gabor.
It would be reassuring if our friend Srinath could prove for himself that the necessary clock buffer is indeed present. We have seen many designs in these forums where the clock buffer was not auto-inserted by the ISE tools. Hence my concern.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-20-2012 10:37 PM
I thank everyone here for extending your help to me,Due to some technical problems my work has been interrupted for now. I would appereciate if you further help me working out the solution after I resume my work.
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-24-2012 02:57 AM
Finally it paid off. The serial transmission protocol is working. There was a fault in the hardware itself, the code was perfectly right. thank you gentlemen for your support. especially Bob and Gabor. i would have been lost without u.
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-24-2012 02:59 AM
To Bob,
I'm a boy by the way, 25 years old. and My name is Srinath Varda.
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-24-2012 05:11 AM
srinathvarda wrote:
Finally it paid off. The serial transmission protocol is working. There was a fault in the hardware itself, the code was perfectly right. thank you gentlemen for your support. especially Bob and Gabor. i would have been lost without u.
Just out of curiosity, once you had the hardware fixed did you need to take out the inversion
on the serial data output?
-- Gabor
Re: small problem in my serial Transmissi on module synthesize d using Verilog continuous ly
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05-24-2012 11:03 PM
Yes, the protocol says that the bits shouldn't be inverted before sending. But due to the technical fault (malfunction of MAX3232) in the hardware I could able to get the characters when inverted before sending. The MAX3232 is suppose to do the invertion of bits. Hence the problem.











