General Technical Discussion

[sunimal123]

Hi,

I am trying to write a test bech code to test my digital system. the FPGA board i am working on don't have any switches etc.. to set as input signals. 

I need to input 16 data lines 50us interveral with a strobe signal to validate data. is there a way come up with test bench code?

Thanks.

[rcingham]

Normally a 'testbench' refers to something used in simulation to test your FPGA/ASIC design, or a part thereof. It may be written in VHDL, (System)Verilog, or any other language that the simulator understands.

Can you describe more fully what environment you are working in?

[joelby]

I'm not entirely sure how you would set such a specific test signal if you did have switches handy (I don't think I could reliably toggle 16 at 50us)

Sometimes I'll use a switch or a push button to activate test/debug modes at certain stages of development. If that's the sort of thing you want to do but can't, you could consider using a 'virtual IO' system - the most obvious one is ChipScope Pro VIO, which allows you to set up virtual switches and LEDs, and also 'For synchronous outputs, provides ability to define a pulse train, which is a 16-cycle train of ones and zeros that run at design speed'

You could also use a human-friendly serial console, possibly with something like PicoBlaze or MicroBlaze, to examine or set your design's internal registers (and thus modes) at low speeds.

Hopefully I'm not too off track from what you were getting at.

[sunimal123]

I am using VHDL in my application. in my digital system i have FIFO to acquire data and then i am reading data to time tag them and then i am sending that data to a another FIFO. From that FIFO i am reading data and writing to a external SRAM chip. Also I am using the ISA bus to transfer data to the CPU.

What i am trying to do is some up with some kind of simulation in XILINX ise. I tried with real signals without any success.

[sunimal123]

Hi,

i forgot to mention i am using ISE 10.1 with Spartan 2 FPGA. Is this Chipscope software support vitual I/O in this version of ISE.

Thanks 

[rcingham]

ChipScope is not a 'simulation' tool. It is for debugging inside the FPGA. Are you trying to simulate?

[sunimal123]

yes i am trying to simulate some parts of my project. since i few digital systems involed in my design i don't think i can simulate all at once.

is there a way to come up with test bench code without uisng switches,  buttons etc...

[joelby]

"Test bench" in the FPGA/ASIC domain usually refers to a simulation that exercises and checks a module. You don't necessarily need to test all of your design at once (with large designs it becomes increasingly infeasible to test every possible input), but you should aim to test individual modules comprehensively. For a guide to writing simulation test benches, I recommend reading XAPP199: Writing Effective Testbenches. You don't have switches and buttons in such a test bench - it's an HDL module that might read in test vectors from a file and compare the output to another file, or just continuously increment the value of an input register and see what happens, or anything else. Hopefully XAPP199 should make their role very clear and give you some inspiration.

In a production design you might have a 'test mode' that runs at power up or on demand and verifies certain aspects of the design (ensuring that peripheral ICs are connected and responding correctly is a good example). You could run through such tests and flash an error LED if something is wrong and/or use a serial console to report on errors in detail. If your user I/O is limited, you could use a serial console to interact with the design to set test modes or change the configuration of your design. JTAG and ChipScope VIO can be used for similar purposes.

Hopefully your FPGA board has at least two spare I/O pins that you can use for RS232, or the JTAG pins are exposed.

[bassman59]

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sunimal123 wrote:

yes i am trying to simulate some parts of my project. since i few digital systems involed in my design i don't think i can simulate all at once.

is there a way to come up with test bench code without uisng switches,  buttons etc...

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You should be able to at least model the important parts of your FPGA's external peripherals and systems.

[sunimal123]

Thanks for your reply. i think i need to read about test benches and try to simulate each module at a time. In my application i am writing data to a FIFO then i read the FIFO and time tags the data and write to aanother FIFO. In order to test the read_fifo module i can probably use test vectors form a file i think.

in your reply you mention using a serial console to test the design. i have planty of unused user i/o pins in my FPGA. could  you please explain lilitle bit more about using user I/O to test the design.

Thanks