Hierarchical Design

[rikusleroux]

Hi guys,

I'm a bit confused on how to constrain the ICAP for Virtex-5. I saw in the partial reconfiguration guide that I should add:

NET “to_icap<*>” MAXDELAY = 15 ns;

NET “from_icap<*>” MAXDELAY = 15 ns;

NET “busy_from_icap” MAXDELAY = 15 ns;

NET “write_to_icap” MAXDELAY = 15 ns;

NET “ce_to_icap” MAXDELAY = 15 ns;

To the user constraint file. However, I can't seem to get it right. Should I replace the net names (such as "to_icap") with my ICAP names? Or are the names given in the guide universal? I tried replacing it with my implementation-names, but it didn't work. It might also be that I have the hierarchy wrong.

[rikusleroux]

Maybe I should mention my architecture:

Top_level -> inst_ICAP_controller -> ICAP_Virtex5_inst

I've tried various of configurations, but for some reason none of the netlists can be found. Can anyone shine some light on this aspect.?

[lamonnis · Accepted solution]

Hello Riskusleroux,

You need to check in the ngc/edif hierarchy which names are used for your ICAP primitive and be sure that signals connected to ICAp have the same names than you described in your VHDL.

For example, my port CE (CE on ICAP) is connected to ce_icap_int. In my UCF, I indicate the following

NET "CONTROLE_RECONF_inst/MACHINE/ce_icap_int" MAXDELAY = 15 ns;


CONTROLE_RECONF_inst is the instanciation of CONTROLE_RECONF in the TOP_LEVEL_FPGA etc. You cannot apply the constraint directly on CE (ICAP CE) but on internal signals that are connected to the ICAP ports.

Also, be careful with signal names, sometimes, Synplify and perhaps XST would rename some signals

Also be careful with simplifications on vectors.

Hope this help

Lamonnis

[rikusleroux]

Hi Lamonnis,

Thanks for the reply. Is there a simple way to view the ngc/edif hierarchy? In your design, what is "MACHINE"?

The signals I have connected to the ICAP is the same as the ICAP port names. Do you think that will cause issues?

Edit: I saw that it is possible to open ngc files in ISE, so I opened the Top_level.ngc and followed the hierarchy to the ICAP_virtex5_inst, but it looks like the signal names are still intact. But still my constraints don't work. My constraints are added as:

NET "inst_ICAPcontroller/ICAP_Virtex5_inst/CE MAXDELAY = 15 ns ;

where "inst_ICAPcontroller" is my instantiation in the Top_level and "ICAP_Virtex5_inst" the name of my ICAP instantiated in "inst_ICAPcontroller". I tried to change the signal names connected to the ICAP controller, but still no change.

Any ideas?

[rikusleroux]

I solved the issue with Lamonnis' help. The hierarchy was wrong. The working constraint is:

NET "inst_ICAPcontroller/CE" MAXDELAY = 15 ns;

Thanks for your help!

[lamonnis]

hello,

MACHINE was the name I gave for the port map that instanciate the entity containing the signal ce_icap_int.

Enjoy that works :)

lamonnis