Hierarchical Design

[gmarchiori]

Hi all,

I have an issue generating the bitstream in a PlanAhead PR project.

When I run bitgen, the DRC phase returns these errors:

Running DRC.
[...]
ERROR:PhysDesignRules:798 - The network <clk_200_0000MHzPLL0> has an antenna.
   Routing is incomplete.
ERROR:PhysDesignRules:798 - The network <clk_400_0000MHzPLL0> has an antenna.
   Routing is incomplete.
ERROR:Bitgen:25 - DRC detected 2 errors and 10 warnings.  Please see the
   previously displayed individual error or warning messages for more details.

The PAR phase is completed without errors (no unrouted nets) and the timings are met.

The same design, implemented completely inside EDK withour PR, gives no errors and produces

correct and functional bitstreams.

Both clocks (clk_200... and clk_400...) have a fanout of 1, and are connected directly from the clock

generator to the PowerPC core (through a BUFG).

With EDK, the routing is correct and the connections are straight, while, at the end of the PR flow

inside planAhead, both clock are connected to the PowerPC core and to the global routing network,

but I think in a wrong way, and hence the DRC error with bitgen.

Note that these two clocks have nothing to do with the PR partitions (they are connected to another clock).

Attached you can find a capture of the fpga editor screen: it shows the routing of one of the two clocks,

from the clock generator (bottom) to the PowerPC (blue box), and the additional path that runs in the

middle of the image from the left side to the right side, where the global clock networks are; in the

white box there's a zoom of the connections between both clocks, colored in yellow, and the global network.

I think this additional path causes the DRC error, since it is not present in the EDK routed design.

Is there a way to prevent such behavior and have a functional bitstream?

Thanks in advance.

Best Regards,

Giacomo

[woodsd]

Hi Giacomo,

I don't believe I've ever seen this issue, and it is hard to say what it happening with the clock routing.  In order to correctly debug, document, and fix this issue, can you please open a webcase with Technical Support:

http://www.xilinx.com/support/clearexpress/websupport.htm

Thanks,

Derrick

[gmarchiori]

Hi Derrick,

I posted a webcase through my boss' account, since I can't access the webcase site.

It's webcase number 850137, and I uploaded some files I hope will help to trace the issue.

Thanks for your help.

Best Regards,

Giacomo

[rbalzli]

Please setenv XIL_PR_VISUAL to one and run map again. This will create an fpga_editor back script in fpga_editor/ClockSpines.scr. This will help us and you visualize any antenna...

[gmarchiori]

Hi rbalzli,

thanks for your hint, but Xilinx gave me a solution through the webcase I opened:

in this particular case, the wires are wrongly routed, but the antennas are not going

to cause any harm, so the DRC errors can be ignored.

Regards,

Giacomo

[rbalzli]

Hi Giacomo,

I know, I was involved in the solution you were given. I just wanted you to have access to XIL_PR_VISUAL for future references.

Good Luck,

Robert Balzli

[anee_anil]

Hi everyone

I got the same error while running partial bit files.

ERROR:PhysDesignRules:798 - The network <dual_ppc_system/clk_400_0000MHzPLL0>
has an antenna. Routing is incomplete.
ERROR:PhysDesignRules:798 - The network <dual_ppc_system/clk_200_0000MHzPLL0>
has an antenna. Routing is incomplete.

Ignore DRC while running partial bit files

-d*

False

 Select don't run DRC

Now you can able to generate bit file.

[jdondo]

I had the same problem and I fix it selecting the antenna in FpgaEditor,  right click, select unroute command and then routing again with Auto route command.

Regards,

Julio