Hierarchical Design

[vinod4corel.com]

Hi all,

I am new to the partial reconfiguration,

I have read in V6 user guide  that we can directly instantiate the ICAP module in our program

ICAP_VIRTEX6_inst  :  ICAP_VIRTEX6
generic  map  (
DEVICE_ID  =>  X"4244093", --  Specifies  the  pre-programmed  Device  ID  value
ICAP_WIDTH  =>  "X8", --  Specifies  the  input  and  output  data  width  to  be  used  with  the
--  ICAP_VIRTEX6.
SIM_CFG_FILE_NAME  =>  "NONE"    --  Specifies  the  Raw  Bitstream  (RBT)  file  to  be  parsed  by  the  simulation
--  model
)
port  map  (
BUSY  =>  BUSY,      --  1-bit  Busy/Ready  output
O  =>  O, --  32-bit  Configuration  data  output  bus
CLK  =>  CLK, --  1-bit  Clock  Input
CSB  =>  CSB, --  1-bit  Active-Low  ICAP  input  Enable
I  =>  I, --  32-bit  Configuration  data  input  bus
RDWRB  =>  RDWRB    --  1-bit  Read/Write  Select  input
);
--  End  of  ICAP_VIRTEX6_inst  instantiation

I want some example design documents with it .

If anyone used them please explain how to use that.

I have a doubt that  which bitstream data we need to give for  that and where it will be placed on the FPGA ?

will this  be applicable for Partial Reconfiguration?

[woodsd]

Yes, you can use ICAP to load in a partial bitstream.  The method of where the partital bitstream get stored (FLASH, SRAM, etc.) and how it get delivered to the FPGA (UART, I2C, PCIe,etc) is all up to the user.  There a couple of examples on xilinx.com that show how to use the ICAP in a PR design.

There is a PR tutorial that uses EDK and the ICAP peripheral to do a partial reconfiguration.  It is located here:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/PlanAhead_Tutorial_Reconfigurable_...

Also, there is a recenlty released appnote that shows how to do a CRC check on the data prior to loading this into ICAP.  The appnote is here:

http://www.xilinx.com/support/documentation/application_notes/xapp887_PRC_EPRC.pdf

[spacegato]

I have the same question but I am not interested in using an embedded processor or the XPS HWICAP wrapper. The designs I have considered for partial reconfiguration (PR) are logic designs that will not use an embedded processor. Therefore, I plan for them to work directly with the ICAP primitive (the Virtex-5, ICAP_VIRTEX5) and not XPS HWICAP. I have searched for instantiation templates, parameter descriptions, code examples that use ICAP_VIRTEX5, and documentation that describe how to use ICAP_VIRTEX5 without a processor driven XPS HWICAP, but I have not found anything that gives this information; the only thing that I have found is a small paragraph in the Virtex-5 UG191 (v3.9.1).

I also need some clarity on the subjects discussed in LogiCORE IP XPS HWICAP (DS586 v5.01a). The document gives the impression that the XPS HWICAP and HWICAP are separate initiates where the XPS HWICAP is a core that provides an interface to the PLB, and the HWICAP is a wrapper to the ICAP_VIRTEX5 primitive that provides registers and an asynchronous FIFO for I/O. If HWICAP is a wrapper for ICAP_VIRTEX5, then would it be best for logic designs to instantiate HWICAP and interact with it instead of directly with ICAP_VIRTEX5? If this is true, is there documentation, other than DS586, that provide instantiation templates, code examples, etc. for using HWICAP in logic designs that do not use an embedded processor? Document DS586 seems to focus on a processor driven design.

[woodsd]

There isn't much information on ICAP.  You might want to look at XAPP887.  This is doing CRC checking on a partial bitstream prior to loading it through ICAP.  There are some timing diagrams, and the reference design has an FSM that talks to ICAP.  This if for Virtex6, but should be very similar to V5 (port names may vary slightly).

http://www.xilinx.com/support/documentation/application_notes/xapp887_PRC_EPRC.pdf

[spacegato]

Thanks.  I'll take a look at it.  I have a question about the difference between ICAP and SelectMAP.  Several documents state that the difference between ICAP and SelectMAP is that ICAP is on the "fabric side."  The way I interpret the "fabric side" difference is that ICAP is implemented as a hard core native to the FPGA or implemented in logic, and that SelectMAP is a configuration interface device external to the FPGA.  However, I haven't found anything that confirms my interpretation (the closest being UG702 v13.2) and also, after reading more about SelectMAP, I'm left with the impression that the SelectMAP interface is not external to the FPGA.  Therefore, leading me to believed that the differences is the driving clock where ICAP is driven internally and SelectMAP is driven from an external clock.  The problem I run into with this idea is the Master/Slave SelectMAP modes where the SelectMAP mode we use determines the direction of CCLK.  Would you please provide some clarity on this subject?  Is SelectMAP a completely external device?  Of course I still intend on using ICAP for PR, i just want to be clear on the differences.  

[lamonnis]

Hello,

SMAP and ICAP are on the "same bus" that means that datas take the same way. In FPGA, you can imagine there is a mux that allows datas to go in the SMAP interface or in ICAP but NEVER in the two components at the same time.

ICAP is never initialized when you start the FPGA that means that the first boot is always in SMAP mode (slave for PR designs). After that you can load you partial bitstreams with SMAP interface by keeping SMAP pins active (there is an option in bitgen).

If you want to use ICAP after first boot to load your partial bitstreams... It is possible, but you will not sleep during many days LOL.

So, my advice is : begin with SMAP :)

Lamonnis

[spacegato]

Ok, so what I probably didn't make clear is that I am building self-reconfiguring PR designs. And, according to several sources that I have read (conference papers, Xilinx documentation, Xilinx PR flow presentation manual, etc.), self-reconfiguring PR designs use ICAP, driven by a embedded microprocessor or a FSM, to load partial bitstreams. What I was asking for in my first post is documentation and example designs that use a FSM to drive ICAP, since I do not intend on implementing PR designs that include an embedded processor. The link that woodsd provided gave me one example, but I would like to see more if there are any.

In addition to the above I wanted more clarity on the difference between SelectMAP and ICAP since the Virtex-5 UG191 states that the only difference is that ICAP is "on the fabric side." After reading other documents, I can now assume that "on the fabric side" means that SelectMAP is driven by an external microprocessor/source, similar to JTAG. However, I'd rather have confirmation of that than just go with my assumption.

What I'm slightly confused about is that, after the initial configuration of the FPGA, you suggest I use SelectMAP instead of ICAP for PR. Did you assume that I would be initiating PR from an external source or is SelectMAP also used for self-reconfiguring PR designs?

[lamonnis]

Hello,

You can check design files from XAPP1100 (Multiboot) which uses ICAP to understand how to control it with a state machine.

For the clarity between SMAP and ICAP, i think xilinx engineers know better than me these interface.

For the functionnality you want to implement, I succeed to do a self reconfiguring PR design on ML507 during my last internship. In fact I had to reprogram the CPLD on the board to control memory signals (XCF32P memory).

If I well remember what I have done, I used Multiboot design files as reference and I adapted them. In SMAP, remove ICAP  et replace ICAP control signal with signals that will control the memory chip on the board.

If you succed for this step, you will realize that you cannot know very precisely when the partial reconfiguration is done. So when you have the control with SMAP, you will try to do the same with ICAP.

Create your own post in the forum because you are not the creator of this post :)

Lamonnis