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Visitor
tamas.gyorfi
Posts: 13
Registered: ‎07-23-2010
0

ICAP - configuration debugging

Hi,

 

Is it possible to use ICAP for configuration debugging if the partial bitstream is actually loaded via a different interface (JTAG)? The most important for my application would be to detect when the partial reconfiguration has ended.

 

How do I have to configure the ports of the ICAP primitive on a Virtex-5 to read the status of the configuration?

 

The way I'm trying is:

 

ICAP_VIRTEX5_inst : ICAP_VIRTEX5
   generic map (
      ICAP_WIDTH => "X32")
   port map (
      BUSY    => open,               -- Busy output
      O           => status,                   
      CE        => '0'                      -- enable data bus
      CLK      => clk_Icap,         -- 100 MHz clock  
      I             => zero,               
      WRITE => '0'                      -- set to "write"
   );

 

,but status(7:4) is always "1001", even when the partial bitstream is loaded.

Are there any other primitves that detect if the partial bitstream is loaded?

 

Thanks in advance,

Tamas

Xilinx Employee
austin
Posts: 3,678
Registered: ‎02-27-2008
0

Re: ICAP - configuration debugging

t,

 

There is only one configuration engine.  JTAg takes precedence.


So if you use ICAP, you are using the engine, and if JTAG comes along, ICAP will "go away" until JTAgG returns control to the engine (a release after use).

 

Look at how xapp864 uses ICAP (with picoBlaze) to see an example of how it has to deal with JTAG commands happening (the application requests, uses, and then releases, and so too must JTAG, or else things just hang, and go nowhere).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Xilinx Employee
austin
Posts: 3,678
Registered: ‎02-27-2008
0

Re: ICAP - configuration debugging

New thought:

 

Place a register in your partial bistream with a value intialized.


That way, in the originbal bitstream, the regsister could have "O" (8 bit ascii capital O).  After the partial bistream is loaded, the register could have "N."

 

After you notice the register has changed, wait a resonable time for the entire partial bistream to finish loading (based on it length, the bit width, and the config clock frequency....plus a few clocks)

Austin Lesea
Principal Engineer
Xilinx San Jose
Regular Contributor
lamonnis
Posts: 84
Registered: ‎01-13-2011
0

Re: ICAP - configuration debugging

I saw that there is a desynch word during SelectMap sequence... because ICAP uses the "same protocol" than SelectMap, perhaps you can try to detect that word (0000000Dh). I haven't tried yet !!!!

Visitor
tamas.gyorfi
Posts: 13
Registered: ‎07-23-2010
0

Re: ICAP - configuration debugging

Thanks for the answer.

 

Does register initialization work if I load a partial bitstream?

 

The PR user guide sais that:

"Unlike a full device configuration, there are no
dedicated functions such as GSR (global set-reset) or GTS (global tri-state) to force logic to
an initial state. Because the logic surrounding a reconfiguring frame is operating during
the reconfiguration, it is impossible to predict the state or activity of the new logic when it
is released for use."

 

How could I make my register to have the value "N" after the partial bitfile is loaded?

 

Thanks,

Tamas

Xilinx Employee
austin
Posts: 3,678
Registered: ‎02-27-2008
0

Re: ICAP - configuration debugging

Tamas,

 

Good catch!  As there will be no GSR, there will be no transfer of bitstream initial values into DFF.

 

Contents of the PR bitstream will get written to LUT, so use a LUTROM to store the new value.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose