03-20-2012 09:32 AM
Is there a way to influence the used LUT-Input of the PROXY LOGIC in the DPR flow? I wan't to unify the interface of two partitions. Using LOC and BEL constraints, the interface looks quite similar, but for some signals, the input of the PROXY LUT differs.
Solved! Go to Solution.
03-20-2012 10:08 AM
I think you can get what you want using the LOCK_PINS constraint. See the 13.4 Constraints Guide, page 158: