Hierarchical Design

[stuellein]

Hi,

Is there a way to influence the used LUT-Input of the PROXY LOGIC in the DPR flow? I wan't to unify the interface of two partitions. Using LOC and BEL constraints, the interface looks quite similar, but for some signals, the input of the PROXY LUT differs.

Thanks, Christian

[woodsd · Accepted solution]

I think you can get what you want using the LOCK_PINS constraint.  See the 13.4 Constraints Guide, page 158:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf

[woodsd]

You may also want to look at the MAP constraint a few pages later (page 162) in the cosntraints guide

[stuellein]

Perfect. The LOCK_PINS constraint worked for me.

thanks a lot for your quick response!

Christian

[alexhip3]

Thanks for this pdf. I have solved some dudes.

Have a nice day :D