Hierarchical Design

[kalte]

Helle everbody,

I am new to the forum, but familiar with FPGAs etc. and I have a question. I would like to change a VHDL constant during runtime and I thought of doing this by partial reconfiguration, sounds a bit strange, I know. My idea is to map the constant to LUT outputs and change the LUTs during runtime by partial reconfiguration. I do not want to use a register for each constant, because I have hundreds of constants that will potentially be changed during runtime and I do not want to spend an access to all these registers.

* is it possible to constrain the implementation tools to map a constant to a LUT?

* any other suggestion to do the job

Regards

Heiko

[gszakacs]

Under normal conditions, a constant does not synthesize into anything, i.e. its value is

used when synthesizing the design, but it does not exist on its own.  Therefore there

are no routes to "connect" the constant to the "loads" and no way to change it at a single

point within the design.

Anything you do to change the constant in circuit will add resources, with the possible

exception of reconfiguring the design.  A partial reconfiguration swapping out all of the

modules that use the constants would be one way to avoid extra resources.

It's not clear to me why you think a LUT takes less resource than a register.  A register

without any write enable consists of just a flip-flop per bit.  You could change the constants

into instantiated registers with INIT constraints.  Then you could go through the chore

of placing these into a reconfigurable region, etc.

You could also use SRL's as storage for you constants like a ROM.  In the case of SRL's

you could just issue a recirculating shift to move through a set of values, or you could use

the SRL's address lines to select one of 16 (or 32 depending on your FPGA architecture)

values.

By the way, partial reconfiguration is not recommended for the casual user of FPGA's.

Search the forums to see how much headache you're in for with PR.

-- Gabor

[kalte]

Hi Gabor,

thanks for the quick reply. Here my comments

Under normal conditions, a constant does not synthesize into anything, i.e. its value is

used when synthesizing the design, but it does not exist on its own.  Therefore there

are no routes to "connect" the constant to the "loads" and no way to change it at a single

point within the design.

--> That is what I found out by try and error and that is the reason I thought of synthesizing the constant into a LUT.

Anything you do to change the constant in circuit will add resources, with the possible

exception of reconfiguring the design.  A partial reconfiguration swapping out all of the

modules that use the constants would be one way to avoid extra resources.

--> adding some resources (registers or LUTs for the constant) is fine, but I do need to change the value from outside the FPGA and I do not want to spend access resources to all the constants, e.g.. large address decoders and multiplexers. The partial reconfiguration seems to be handy.

It's not clear to me why you think a LUT takes less resource than a register.  A register

without any write enable consists of just a flip-flop per bit.  You could change the constants

into instantiated registers with INIT constraints.  Then you could go through the chore

of placing these into a reconfigurable region, etc.

--> the problem with registers from what I know is, that you can set a new initial value by partial reconfiguration, but afterwards you need to reset the area to take over the new value into the register. A reset is not possible in this case, the rest of the design needs to keep running. That is why I thought of a LUT instead of register to hold the constant.

You could also use SRL's as storage for you constants like a ROM.  In the case of SRL's

you could just issue a recirculating shift to move through a set of values, or you could use

the SRL's address lines to select one of 16 (or 32 depending on your FPGA architecture)

values.

--> Your suggestion sounds interessting, but there is not a set of values for the constant. During runtime I need to change the constant to an arbitrary value. However the SRL could be a ressource efficient way to acces the constants if I put all the constants in one big shift register.

By the way, partial reconfiguration is not recommended for the casual user of FPGA's.

Search the forums to see how much headache you're in for with PR.

--> You are right (years of pain in research work), but the topic is interesting.

From you answers, I assume that there is no way to constrain the tools, to use LUTs for constants? Is it possible to instanciate LUTs directly within my VHDL code and keep the tools from optimizing the LUTs into real constants?

Regards

Heiko

[gszakacs]

Realizing an arbitrary set of constants using partial reconfiguration becomes a problem

because you'll need to run through the ISE tools for each new constant set.  The idea of

using a long shift register for your constants is probably better, especially if you can live with

the time it takes to re-load the shift register.  Otherwise you'd need two sets of registers,

one to shift and another for parallel load so the constants update all at once.  This is sort

of the idea with reconfiguration, only it would be much faster.  There's an intermediate

approach that uses SRL's for shifting data in, then because the SRL's don't have a parallel

output, you would then shift all of the SRL's into the actual constant registers.  In this approach

the constant registers would be shifting for 16 or 32 cycles only (the depth of one individual

SRL) rather than the whole time the update is taking place.

- Gabor

[luke.skywalker]

You take a look to the library guide for hdl designs, for e.g http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/virtex5_hdl.pdf. Those give you a good overview over the device primitives you can instantiate within your code. If you scroll down to page 192 in the document you can see how you can instantiate a LUT. The rest is up to you.

Code example

Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT6: 6-input Look-Up Table with general output
--       Virtex-5/6, Spartan-6
-- Xilinx HDL Libraries Guide, version 11.2
LUT6_inst : LUT6
generic map (
   INIT => X"0000000000000000") -- Specify LUT Contents
port map (
O => O,  -- LUT general output
I0 => I0, 
I1 => I1, 
I2 => I2, 
I3 => I3, 
I4 => I4, 
I5=>I5
);