Hierarchical Design

[limab_erik]

Hi,

After some testing and looking through this forum and the different Xilinx documents, I get the impression that re-using PAR results with partitions is not possible for the Spartan 3 family (a xpartition.pxml file is needed for that and that is not supported for the Spartan 3 family). Is my understanding correct?

As a follow up question I am wondering if it is correct that the black-box approach (re-using the ngc netlist file) that is supported for the Spartan 3 family only preserves synthesis results and not the placement or routing of the components? In other words that approach does not help me a lot to meet timing, correct?

Is there any way of importing/reusing the ncd output-file from PAR for modules with critical timing?

I have tried using smartguide and it helps but it does not fulfill all my needs.

Thanks

Erik

[woodsd]

You cannot use a partition.pxml file to invoke "Incremental XST" for Spartan-3, but it is supported for the implementation tools (ngdbuild, map, par).  You need to run bottom-up synthesis (or equivalent) to get separate nestlits for your partitions, and then you can use partitions for implementation.  

For more information on running the implementation flow command line or through PlanAhead (netlist project only for S3), reference the following document:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/Hierarchical_Design_Methodology_Gu...

[limab_erik]

Thanks, I have done some testing and made some progress. But I haven't got all bits and pieces together for the bottom-up synthesis flow in my command line scripts. Here are some follow up questions:

My goal with design preservation is to deliver a placed and routed component to my customer. Preferable they should not need my HDL sourcecode.

1. Is the xpartition.pxml file used along with the -sd swithc in NGDBuil?

2. Is it correct that there must exist a xpartition.pxml file in the directory where I want to import my pre-PARed component from and that it has to be a copy of the xpartition.pxml file in the top-level project?

3. Is there a good starting-point (xapp, wp, ug etc) for a bottom up XST flow?

I have managed to import PAR results from a different project (atleast placement confirmed with PlanAhead). But it only works as long as the projects are identical. If I remove the HDL source files for my sub-module from my top-level project NGDBuild fails.

Cheers

/Erik

[woodsd]

1. Is the xpartition.pxml file used along with the -sd swithc in NGDBuil?

 No.  There is no switch for the PXML file.  It has to be called "xpartition.pxml", and it has to be located in the directory where the implementaiton tools are invoked.  If these requirements are met then it will be picked up automatically, and you will see a partitions summary at the end of each report file (BLD, MPR. PAR).  You have to use partitions starting at NGDBuild (you can't just add a PXML in for Map or Par).

2. Is it correct that there must exist a xpartition.pxml file in the directory where I want to import my pre-PARed component from and that it has to be a copy of the xpartition.pxml file in the top-level project? 

When you implement your partitions initially, the PXML file will exist, obviously.  You should then export (copy) those results to another directory for safe keeping.  The HD Meth. Guide lists the required files (*_prev_*) files the "xpartition.pxml.  The new implementation run that will import these results will also have a PXML (that sets the partitions to import, and sets up the import directory).  When the partitions are imported the tools use both PXML files (current one, and the one in the export directory) to make sure you aren't trying to import a partition that didn't exist the export design, etc.

3. Is there a good starting-point (xapp, wp, ug etc) for a bottom up XST flow?

Not that I'm aware of, but there isn't that much too it.  Here are the basics:
a. Create a synthesis project for each  module you want an netlist for (Top, Partition A, Partition B). 

b. For the Top synthesis, you will need black box definitions for Partition A and Partition B

c. For Partition A and Partition B you will need to turn off IO buffer insertion.  See user guide for whatever synthesis tool you are using

d. If you want IO in Partition A or Partition B, you need to manually instantiate them.  

e. If IO buffers do exist in Partition A or Partition B, you need to turn of the insertition for the Top level synthesis for these specific ports.  This means you leave the global IO insertion on for Top, but set attributes for individual ports.  For XST this is the BUFFER_TYPE=NONE attribute (Verilog is (* BUFFER_TYPE=NONE *) before each signal declaration in Top.v

Once you get a netlist for Top, A, and B, you should run these through NGDBuild in a non-partition flow just to make sure everything is okay (no dual buffers, etc.).

[woodsd · Accepted solution]

And for the NGDBuild failures.... I'm sure what is happenning here.  I think you need to setup the bottom up synthesis flow, run synthesis outside of PlanAhead, and then create a netlist project.  You should be good to go from then on as long as you don't rerun synthesis.  If you do resynthesis a module, you'll need to reimplement the associated partition.

[limab_erik]

Finally managed to get it working the way I want!

I now have three projects with the same hierarchy. Each of them implementing their part of the design while the other modules are empty blackboxes. My top project can then put them all together with no knowledge about the submodules source files.

My mistake was that my top project did not have full control of the submodules netlists. I forgot copying them to the location where the tools for top-level implementation was invoked (and I forgot keeping them up to date).

Thanks for your support.

/Erik