Hierarchical Design

[pixie_sunky]

Hi everyone

I woud like to use a BUFR to drive clock signal and utilise the regional clock resources to perform PR.  I instantiated the BUFR primitive in the top file and performed PR. Everying worked fine and it can meet the timing requirements. However when I open the implemented design using FPGA editor, I found the clock routings used is shown in the Figure below.

It seems the design used local clock routing instand of regional clock resources although the BUFR is used ( cause I know the regional clock is a dedicated clock resources).

I instantiated the BUFR as follow:

Inst1_BUFR : BUFR

port map (
I => clk,
CE=> '1',
CLR => '0',
O => clk_int
);

Can some tell me what is the problem of the design using the regional clock resources???

If want to use regional clock resources in the process of PR, what should I do??

Cheers

[woodsd]

What you are describing sounds correct.  As a test, I just ran the PR Tutorial Design and replaced the BUFG with a BUFR just as you instantiated it below.  My resulting BUFR routing was correct (see below).  Double check your HDL and make sure everything is connected as you expect, or use PlanAhead's schematic viewer to look at the connections in the netlist.