Hierarchical Design

[pixie_sunky]

Hi everyone

I did some examples to implment multiple types of FIR filters with Partial Reconfiguration. I did every step successfully as the Partial Reconfiguration document tells, including successful PR Verify Process. I also add the ChipScope to verify filter tap coefficients by downloading different partial bitstream.

The Problem I found is that the verification on ChipScope does work  from time to time!!!. That means when I change the order to download partial bitstream, Sometimes I can get the correct results, however Sometimes, I can only get the Zero from ChipScope. It looks like the PR Project does not work or fail. 

For examples, I have 3 partial bitstreams (1_PR.bit, 2_PR.bit and 3_PR.bit) and 3 full bitstream (1.bit, 2.bit and 3.bit). When I want to veirfy the PR results by ChipScope, I have to download 1.bit file and download 2_PR.bit, verify results, download 3_PR.bit and results and finally download 1_PR.bit to verify. At this moment, I couldn't get correct results but zero from ChipScope sometimes but not always.  Also I tried to download 2.bit first and download 3_PR.bit, 1_PR.bit and 2_PR.bit step by step, I am not sure every time I can get correct results.....

So I am confused, Did I do somthing wrong when doing PR Project?? Does anyone have the same experience with me?? 

I tried many times and I found if I have 2 partial bitstreams, whatever I choose the order, Every time I am sure it can work successfully. However, if I have 3, I am not sure.

Does that mean when you increase your reconfigurable modules more than two modules, the PR cann't guarantee the stability?? or there is something wrong with ChipScope??

Plus, I am using Virtex 5 lx110t board and ISE 13.1 suite

Cheers

[woodsd]

It's hard to guess what might be going on here.  However, having multiple partitial bitfiles for each reconfigurable block does not make it less stable.

As an experiement you could download 1.bit (verify chipscope), followed by 2_PR.bit (verify chipscope), and then continue to download 2_PR.bit and see if you can disrupt the system.  If the partial reconfiguration of 2_PR.bit work consistently everytime, then maybe you have a timing issue or design issue in on of the other variants (ie. 3_PR.bit).  If 2_PR.bit eventually fails, then you may have a problem in design as a whole (gated clock, bad reset logic, etc...), or a problem with the configuration interface (does the partial reconfiguration complete successfully?  Does doing another partial reconfiguration of the same partial bitfile fix the chipscope output once it goes to '0's?).  

Also do have a system reset?  Once the Chipscope output goes to "0"s, can you reset and get correct output?

[austin]

p_s,

I would examine the design in PlanAhead, and check that each pr block is properly constrained in area.  Common problems are that the design is overlapping with something else.  As well, ChipScope must be included in whatever partition you are loading in, or else it can't connect to the signals you wish to observe (ChipScope should not be in the base module, as ChipScope needs to be part of whatever design you are loading).

If you have ChipScope is in the base module, and you load another module also with ChipScope, I am sure that now things get very confusing:  how does one ChipScope deal with another copy of itself, both loaded in?  I suspect that the last Chipscope loaded gets to use the JTAG port, but there is only one set of routes to the JTAG hardware, so this could get very ugly, and ChiScope becomes non-functional.

You can also look at the .ncd files in FPGA_Editor.

If it were me, I would place ChipScope only in the pr modules, and remove it as soon as evrything is debugged and working.

[pixie_sunky]

Many Thanks for answering the questions

I also tried to add the reconfigurable filters as a peripheral and connect it with MicroBlaze without ChipScope. I tested results with Hyper Terminal, these kinds of problems happend from time to time!!  I am very sure every design step is sucessfully without any timing, area constraints errors.

I will try to put the ChipScope into the Reconfigurable Partition and test results 

Cheers