Hierarchical Design

[hallolo]

Hello

Iam not sure if it is possible or not to infer Block RAMs from Fifio's. The issue is that i have an RP region which contain 15 Fifos and 15 BRAMs , and i has an RM which required 17 BRAM's, is it possbile to allow the tool to use two of the 15 Fifios as BRAMs? Currently when i try this i get an error that there are no enough resources for this implementation, so i just wanted to learn if an option exist for such case?

Thanks

Hallolo

[woodsd]

I think what you are asking about is how to control how many BRAM/FIFO resources get inferred.  This should be controlled by synthesis.  XST has several options for BRAM inference and utilzation.  For example look at the constraint BRAM_UTILIZATION_RATION on page 385 of the XST User's Guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/xst_v6s6.pdf

The BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO) constraint defines the
number of block RAM components that XST must not exceed during synthesis.

You can also put individual constraints on each RAM to get fine control (see RAM_STYLE). 

[gszakacs]

You have to watch out for double-counting resources.  There are some resources that can be

configured two ways.  Until you use them, you will see both resources listed as available.  In

fact the 15 FIFO's and 15 BRAM's are the same 15 blocks in the FPGA.  You don't get both, you

only get 15 total FIFO's + BRAM's.

Another place you see this is 36Kb BRAM's and 18Kb BRAM's.  If you had 15 available 36Kb

BRAM's you would also see 30 (2 * 15) available 18Kb BRAM's.  Again these 30 18Kb BRAM's

are the same blocks that make up the 15 36Kb BRAM's.

-- Gabor

[hallolo]

Thanks Gabror  for the reply

well i thought that some of those pink sites in the chip ( when viewing the device in PlanAhead) can either be used as RAMB 16 or as a FIFO 16 since each identified with specific type. I seem to have had some confusion with this thinking that there are two sites in each of those pink columns one is a FIFIO and the other is RAM16, does what you say imply that the two sites in those pink column can both be used as FIFO or both as RAM16? or the two sites are actually one instance either the RAMB16 or the other?

Regards

Hallolo 

[gszakacs]

I would suggest looking at the User Guide or Memory User Guide for your FPGA.  Basically the

block RAM and FIFO logic are all common to a single site in the FPGA.   You can use the BRAM

with or without the FIFO logic.  However the FIFO logic is only an address and flag generator,

so you still use the (same) BRAM if you use the FIFO.  You can't have both BRAM and FIFO

from the same site.

-- Gabor

[hallolo · Accepted solution]

Thank Gabor, i appreciate your help

regards

Hallolo