12-15-2009 03:05 AM - edited 12-30-2009 01:55 AM
When I partially reconfigure a V5 FPGA with a differential core, the initial register states are not set according the design. (Fe. a reg init value should be 0xAA and i read back 0xFF).
I generate the core with:
bitgen -w -d -g Readback -g ActiveReconfig:Yes -g Persist:Yes -r reference.bit $(NCDFILE) $(BITFILE)
Tried with persist:Off too...
If I set ActiveReconfig to NO, then the registers are set correctly, but i cant use ICAP to configure the device through PCIexpress...
The partial core is clocked with a BUFGCE, so i disable the partial clock while reconfiguration and enable it afterwards.
Is there a bitgen switch to solve this problem, or should i stick to a user reset signal?
Ps. manually editing the bit file and adding a GRESTORE command at the end didn't solve the problem.
Solved! Go to Solution.
12-30-2009 01:54 AM
Does someone know an example design/description of difference based-partial reconfiguration?
Step-by-step instructions would be nice.
I think I only have problems with programming file generation (see my problem above).